FinFET-based Dynamic Power Management of On-chip Interconnection Networks through Adaptive Back-gate Biasing

Chun Yi Lee, Niraj K. Jha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

16 Scopus citations

Abstract

On-chip interconnection networks are fast becoming significant power-consumers in high-performance chip multiprocessors (CMPs). Increased power consumption leads to more heat, adversely degrades system reliability, and may increase the cost of cooling IC packages. This situation becomes even worse as bulk CMOS scales further into the nanometer regime because of excessive leakage power due to short-channel effects. In this paper, we explore the use of FinFETs, which are promising substitutes for bulk CMOS at the 32nm node and beyond, to design on-chip network routers. We present a detailed design of a variable pipeline stage router (VPSR) targeted at FinFET technology. We employ a dynamic power management scheme, which we call adaptive back-gate biasing (ABGB), for FinFET implementations. We evaluate VPSR and ABGB on a simulation platform specifically designed for power and performance simulations for FinFET-based interconnection networks. The results show that VPSR is able to successfully adapt its power consumption to incoming traffic, with a resultant 20% reduction in power at almost no impact on latency.

Original languageEnglish (US)
Title of host publication2009 IEEE International Conference on Computer Design, ICCD 2009
Pages350-357
Number of pages8
DOIs
StatePublished - Dec 1 2009
Event2009 IEEE International Conference on Computer Design, ICCD 2009 - Lake Tahoe, CA, United States
Duration: Oct 4 2009Oct 7 2009

Publication series

NameProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
ISSN (Print)1063-6404

Other

Other2009 IEEE International Conference on Computer Design, ICCD 2009
CountryUnited States
CityLake Tahoe, CA
Period10/4/0910/7/09

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Keywords

  • FinFETs
  • GARNET
  • Interconnection network
  • ORION
  • VPSR
  • Voltage generator

Fingerprint Dive into the research topics of 'FinFET-based Dynamic Power Management of On-chip Interconnection Networks through Adaptive Back-gate Biasing'. Together they form a unique fingerprint.

  • Cite this

    Lee, C. Y., & Jha, N. K. (2009). FinFET-based Dynamic Power Management of On-chip Interconnection Networks through Adaptive Back-gate Biasing. In 2009 IEEE International Conference on Computer Design, ICCD 2009 (pp. 350-357). [5413133] (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors). https://doi.org/10.1109/ICCD.2009.5413133