Recently, FinFETs have emerged as promising substitutes for conventional CMOS because of their superior control of short-channel effects and processing scalability. Nevertheless, lithographic constraints, difficulties in workfunction engineering, supply voltage variations, and temperature nonuniformity across the FinFET integrated circuit may lead to process, supply voltage, and temperature (PVT) variations, which are manifested as large spreads in delay and leakage. In this paper, we present FinCANON, an integrated framework for the simulation of power, delay, as well as PVT variations of FinFET-based caches and on-chip networks. FinCANON consists of CACTI-PVT and ORION-PVT that model caches and on-chip networks, respectively. We have developed a FinFET design library to model the circuit-level characteristics as well as their variation trends with respect to various PVT parameters for FinFET logic gates and memory cells, using accurate device simulation. With a statistical static timing analysis technique and macromodel-based methodology, we have also derived PVT variation models for delay and leakage, considering spatial correlations, to characterize the impact of PVT variations on FinFET-based caches and networks-on-chip (NoCs). In addition, we incorporate voltage generators in the FinFET design library to model back-gate biasing of FinFETs. The cache and NoC models are significantly enhanced to be more modular and scalable. We present results for various FinFET design styles and show that mixing different styles may be a promising strategy for optimizing delay and leakage of caches and NoCs.
|Original language||English (US)|
|Number of pages||14|
|Journal||IEEE Transactions on Very Large Scale Integration (VLSI) Systems|
|State||Published - May 2014|
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering
- PVT variations.