Fault-tolerant computing using a hybrid nano-CMOS architecture

Muzaffer O. Simsir, Srihari Cadambi, Franjo Ivančić, Martin Roetteler, Niraj Kumar Jha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

Architectures based on nanoscale molecular devices are attracting attention for replacing CMOS architectures at the end of the semiconductor roadmap. The two most promising nanotechnologies, according to ITRS, are silicon nanowires and carbon nanotubes. Although they offer unmatched densities for building logic, interconnect and memory, they suffer from very defect-prone manufacturing processes. This is further exacerbated by testing complexities where it is nearly impossible to detect all defects in a large nanoscale chip. Furthermore, the small structures in nanoscale architectures are susceptible to transient faults which can produce arbitrary soft errors. As a result, fault tolerance is necessary to make nanoscale architectures practical and realistic. We propose an architecture that can tolerate a large number of undetected manufacturing faults as well as a large rate of transient faults. Our architecture is characterized by multiple levels of redundancy and majority voting to correct errors caused by such faults. A key aspect of the architecture is that it contains a judicious balance of both nanoscale and traditional CMOS components. A companion to the architecture is a compiler with heuristics tailored to quickly and compactly map logic onto partially defective components. Experimental results demonstrate the efficacy of the architecture.

Original languageEnglish (US)
Title of host publicationProceedings - 21st International Conference on VLSI Design, VLSI DESIGN 2008
Pages435-440
Number of pages6
DOIs
StatePublished - Jul 25 2008
Event21st International Conference on VLSI Design, VLSI DESIGN 2008 - Hyderabad, India
Duration: Jan 4 2008Jan 8 2008

Publication series

NameProceedings of the IEEE International Frequency Control Symposium and Exposition

Other

Other21st International Conference on VLSI Design, VLSI DESIGN 2008
CountryIndia
CityHyderabad
Period1/4/081/8/08

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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