FAULT-TOLERANCE DESIGN IN REAL-TIME VLSI ARRAY PROCESSORS.

S. Y. Kung, C. W. Chang, C. W. Jen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

Three important fault-tolerance issues are treated: (1) how to minimize the testing, reconfiguration, and roll-back time; (2) how to deal effectively with transient faults; and (3) how to allocate spare processing elements (PEs). To improve the overall reliability performance, a reconfiguration algorithm which is distributively executed by all PEs is proposed. This reconfiguration algorithm can also be applied to transient faults. The timing analysis for systolic and wave-front arrays are discussed. A partition and cascade scheme for spare PE distribution is proposed that should significantly improve the system reliability.

Original languageEnglish (US)
Title of host publicationConference Proceedings - Annual Phoenix Conference
PublisherIEEE
Pages110-115
Number of pages6
ISBN (Print)0818607653
StatePublished - Jan 1 1987
Externally publishedYes

Publication series

NameConference Proceedings - Annual Phoenix Conference

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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  • Cite this

    Kung, S. Y., Chang, C. W., & Jen, C. W. (1987). FAULT-TOLERANCE DESIGN IN REAL-TIME VLSI ARRAY PROCESSORS. In Conference Proceedings - Annual Phoenix Conference (pp. 110-115). (Conference Proceedings - Annual Phoenix Conference). IEEE.