Fault modeling for FinFET circuits

Muzaffer O. Simsir, Ajay Bhoj, Niraj Kumar Jha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

31 Scopus citations

Abstract

FinFETs are expected to supplant planar CMOS field-effect transistors (FETs) in the near future, owing to their superior electrical characteristics. From a circuit testing viewpoint, it is unclear if CMOS fault models are comprehensive enough to model all defects in FinFET circuits. In this work, we address the above problem using mixed-mode Sentaurus TCAD device simulations and demonstrate that while faults defined for planar MOSFETs show significant overlaps with FinFETs, they are insufficient to encompass all regimes of operation. Results indicate that new fault models are needed to adequately capture the behavior of logic gates based on independent-gate FinFETs with opens on the back gate, and shorted-gate FinFETs which have been accidentally etched into independent-gate structures.

Original languageEnglish (US)
Title of host publicationProceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010
Pages41-46
Number of pages6
DOIs
StatePublished - Aug 24 2010
Event2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010 - Anaheim, CA, United States
Duration: Jun 17 2010Jun 18 2010

Publication series

NameProceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010

Other

Other2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010
CountryUnited States
CityAnaheim, CA
Period6/17/106/18/10

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Keywords

  • Delay
  • Fault model
  • FinFET
  • Leakage

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  • Cite this

    Simsir, M. O., Bhoj, A., & Jha, N. K. (2010). Fault modeling for FinFET circuits. In Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010 (pp. 41-46). [5510927] (Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010). https://doi.org/10.1109/NANOARCH.2010.5510927