Faster checkpointing with N+1 parity

James S. Plank, Kai Li

Research output: Chapter in Book/Report/Conference proceedingConference contribution

57 Scopus citations


This paper presents a way to perform fast, incremental checkpointing of multicomputers and distributed systems by using N + 1 parity. A basic algorithm is described that uses two extra processors for checkpointing and enables the system to tolerate any single processor failure. The algorithm's speed comes from a combination of N + 1 parity, extra physical memory, and virtual memory hardware so that checkpoints need not be written to disk. This eliminates the most time-consuming portion of checkpointing. The algorithm requires each application processor to allocate a fixed amount of extra memory for checkpointing. This amount may be set statically by the programmer, and need not be equal to the size of the processor's writable address space. This alleviates a major restriction of previous checkpointing algorithms using N + 1 parity [28]. Finally, we outline how to extend our algorithm to tolerate any m processor failures with the addition of 2m extra checkpointing processors.

Original languageEnglish (US)
Title of host publicationDigest of Papers - International Symposium on Fault-Tolerant Computing
PublisherPubl by IEEE
Number of pages10
ISBN (Print)0818655224
StatePublished - Jan 1 1994
Externally publishedYes
EventProceedings of the 24th International Symposium on Fault-Tolerant Computing - Austin, TX, USA
Duration: Jun 15 1994Jun 17 1994


OtherProceedings of the 24th International Symposium on Fault-Tolerant Computing
CityAustin, TX, USA

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Engineering(all)


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