Fast software cache design for network appliances

Dong Zhou, Huacheng Yu, Michael Kaminsky, David G. Andersen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The high packet rates handled by network appliances and similar software-based packet processing applications place a challenging load on caches such as flow caches. In these environments, both hit rate and cache hit latency are critical to throughput. Much recent work, however, has focused exclusively on one of these two desiderata, missing opportunities to further improve overall system throughput. This paper introduces Bounded Linear Probing (BLP), a new cache design optimized for network appliances. BLP works well across different workloads and cache sizes by balancing between hit rate and lookup latency. To accompany BLP, we also present a new, lightweight cache eviction policy called Probabilistic Bubble LRU that achieves near-optimal cache hit rate (assuming the algorithm is offline) without using any extra space. We make three main contributions: a theoretical analysis of BLP, a comparison between existing and proposed cache designs using microbenchmarks, and an end-to-end evaluation of BLP in the popular Open vSwitch (OvS) system. Our end-to-end experiments show that BLP is effective in practice: replacing the microflow cache in OvS with BLP improves throughput by up to 15%.

Original languageEnglish (US)
Title of host publicationProceedings of the 2020 USENIX Annual Technical Conference, ATC 2020
PublisherUSENIX Association
Pages657-671
Number of pages15
ISBN (Electronic)9781939133144
StatePublished - 2020
Event2020 USENIX Annual Technical Conference, ATC 2020 - Virtual, Online
Duration: Jul 15 2020Jul 17 2020

Publication series

NameProceedings of the 2020 USENIX Annual Technical Conference, ATC 2020

Conference

Conference2020 USENIX Annual Technical Conference, ATC 2020
CityVirtual, Online
Period7/15/207/17/20

All Science Journal Classification (ASJC) codes

  • Computer Science(all)

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