TY - GEN
T1 - Fast parallel table lookups to accelerate symmetric-key cryptography
AU - Fiskiran, A. Murat
AU - Lee, Ruby B.
PY - 2005
Y1 - 2005
N2 - Table lookups are one of the most frequently-used operations in symmetric-key ciphers. Particularly in the newer algorithms such as the Advanced Encryption Standard (AES), we frequently find that the greatest fraction of the execution time is spent during table lookups, varying between 34% and 72% for the five representative ciphers we consider: AES, Blowfish, Twofish, MARS, and RC4. In order to accelerate and parallelize these table lookups, we describe a new parallel table lookup (ptlu) instruction. Our synthesis results indicate that such an instruction can be added to a basic RISC processor with no cycle time impact. We compare the performance of the ptlu instruction with the speedups available through more conventional architectural techniques such as multiple-issue execution. We find that the performance benefits of using the ptlu instruction can be far higher than increasing the number of instructions executed per cycle in superscalar or VLIW processors.
AB - Table lookups are one of the most frequently-used operations in symmetric-key ciphers. Particularly in the newer algorithms such as the Advanced Encryption Standard (AES), we frequently find that the greatest fraction of the execution time is spent during table lookups, varying between 34% and 72% for the five representative ciphers we consider: AES, Blowfish, Twofish, MARS, and RC4. In order to accelerate and parallelize these table lookups, we describe a new parallel table lookup (ptlu) instruction. Our synthesis results indicate that such an instruction can be added to a basic RISC processor with no cycle time impact. We compare the performance of the ptlu instruction with the speedups available through more conventional architectural techniques such as multiple-issue execution. We find that the performance benefits of using the ptlu instruction can be far higher than increasing the number of instructions executed per cycle in superscalar or VLIW processors.
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M3 - Conference contribution
AN - SCOPUS:24744455038
SN - 0769523153
SN - 9780769523156
T3 - International Conference on Information Technology: Coding and Computing, ITCC
SP - 526
EP - 531
BT - Proceedings ITCC 2005 - International Conference on Information Technology
A2 - Selvaraj, H.
A2 - Srimani, P.K.
T2 - ITCC 2005 - International Conference on Information Technology: Coding and Computing
Y2 - 4 April 2005 through 6 April 2005
ER -