In this paper, we present a power estimation technique for control-flow intensive designs that is tailored towards driving iterative high-level synthesis systems, where hundreds of architectural trade-offs are explored and compared. Our method is fast and relatively accurate. The algorithm utilizes the behavioral information to extract branch probabilities, and uses these in conjunction with switching activity and circuit capacitance information, to estimate the power consumption of a given architecture. We test our algorithm using a series of experiments, each geared towards measuring a different indicator. The first set of experiments measures the algorithm's accuracy when compared to the actual circuit power. The second set of experiments measures the average tracking index, and tracking index fidelity for a series of architectures. This index measures how well the algorithm makes decisions when comparing the relative power consumption of two architectures contending as low-power candidates. Results indicate that our algorithm achieved an average estimation error of 11.8% and an average tracking index of 0.95 over all examples.
|Published - Jan 1 1998
|Proceedings of the 1998 International Symposium on Low Power Electronics and Design - Monterey, CA, USA
Duration: Aug 10 1998 → Aug 12 1998
|Proceedings of the 1998 International Symposium on Low Power Electronics and Design
|Monterey, CA, USA
|8/10/98 → 8/12/98
All Science Journal Classification (ASJC) codes