Fast FinFET Device Simulation under Process-Voltage Variations Using an Assisted Speed-Up Mechanism

Sourindra Chaudhuri, Ajay N. Bhoj, Debajit Bhattacharya, Niraj K. Jha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations


The emergence of nonplanar Fin FETs as an alternative to planar CMOS has necessitated a fresh look at process and device simulation. However, process and device simulation times for characterizing Fin FETs have become a major bottleneck in this effort because of the structural complexity of these transistors. In prior work, it has been shown how process simulated Fin FET structures can be derived, at a one-time process simulation cost, that can then be used to perform 3D device simulation. Though this improves CPU time by an order of magnitude over process simulation, 3D device simulation remains quite CPU time-intensive due to the need to thoroughly characterize the device and logic cell library under process voltage (PV) variations, which requires a huge number of device simulations. To address this major problem, we show that the states obtained from quasi-stationary (QS) device simulation of a nominal device can assist simulation of similar devices under variations in gate length (LG), fin thickness (TSI), and gate-oxide thickness (TOX). We show that both the off-current (IOFF) and on-current (ION) of an n/pFin FET can be obtained without any compromise in accuracy, under PV variations, using the proposed assisted mechanism at 5-22× lower simulation time depending on the parameter of interest, through 3D device simulation. It has been shown earlier that 3D device simulation can be sped up significantly by performing 2D device simulation on the Fin FET cross-section using a gate under lap adjustment methodology, with a minor compromise in accuracy. We now show that combining the proposed assisted mechanism with adjusted 2D cross-sections enables us to characterize Fin FET devices very fast (244-8654× lower simulation time) with only a minor loss in accuracy (0-4.93% error), depending on the variation type and parameter of interest. We also demonstrate that this mechanism remains viable for obtaining leakage data of Fin FET logic gates under PV variations. We observe 10742-16560× reduction in simulation time with an 0.45-3.87% error range for obtaining leakage data of Fin FET inverters, NAND and NOR gates of various sizes.

Original languageEnglish (US)
Title of host publicationProceedings - 29th International Conference on VLSI Design, VLSID 2016 - Held concurrently with 15th International Conference on Embedded Systems
PublisherIEEE Computer Society
Number of pages6
ISBN (Electronic)9781467387002
StatePublished - Mar 16 2016
Event29th International Conference on VLSI Design, VLSID 2016 - Kolkata, India
Duration: Jan 4 2016Jan 8 2016

Publication series

NameProceedings of the IEEE International Conference on VLSI Design
ISSN (Print)1063-9667


Other29th International Conference on VLSI Design, VLSID 2016

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering


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