TY - GEN
T1 - Fast enhancement of validation test sets to improve stuck-at fault coverage for RTL circuits
AU - Lingappan, L.
AU - Gangaram, V.
AU - Jha, Niraj Kumar
AU - Chakravarty, S.
PY - 2007/12/1
Y1 - 2007/12/1
N2 - A digital circuit usually comprises a controller and datapath. The time spent for determining a valid controller behavior to detect a fault usually dominates test generation time. A validation test set is used to verify controller behavior and, hence, it activates various controller behaviors. In this paper, we present a novel methodology wherein the controller behaviors exercised by test sequences in a validation test set are reused for detecting faults in the datapath. A heuristic is used to identify controller behaviors that can justify/propagate pre-computed test vectors/responses of datapath register-transfer level (RTL) modules. Such controller behaviors are said to be compatible with the corresponding precomputed test vectors/responses. The heuristic is fairly accurate, resulting in the detection of a majority of stuck-at faults in the datapath RTL modules. Also, since test generation is performed at the RTL and the controller behavior is predetermined, test generation time is reduced. For microprocessors, if the validation test set consists of instruction sequences then the proposed methodology also generates instruction-level test sequences.
AB - A digital circuit usually comprises a controller and datapath. The time spent for determining a valid controller behavior to detect a fault usually dominates test generation time. A validation test set is used to verify controller behavior and, hence, it activates various controller behaviors. In this paper, we present a novel methodology wherein the controller behaviors exercised by test sequences in a validation test set are reused for detecting faults in the datapath. A heuristic is used to identify controller behaviors that can justify/propagate pre-computed test vectors/responses of datapath register-transfer level (RTL) modules. Such controller behaviors are said to be compatible with the corresponding precomputed test vectors/responses. The heuristic is fairly accurate, resulting in the detection of a majority of stuck-at faults in the datapath RTL modules. Also, since test generation is performed at the RTL and the controller behavior is predetermined, test generation time is reduced. For microprocessors, if the validation test set consists of instruction sequences then the proposed methodology also generates instruction-level test sequences.
UR - http://www.scopus.com/inward/record.url?scp=48349089998&partnerID=8YFLogxK
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U2 - 10.1109/VLSID.2007.82
DO - 10.1109/VLSID.2007.82
M3 - Conference contribution
AN - SCOPUS:48349089998
SN - 0769527620
SN - 9780769527628
T3 - Proceedings of the IEEE International Conference on VLSI Design
SP - 504
EP - 509
BT - Proceedings - 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems
T2 - 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems, VLSID'07
Y2 - 6 January 2007 through 10 January 2007
ER -