Fast enhancement of validation test sets for improving the stuck-at fault coverage of RTL circuits

Loganathan Lingappan, Vijay Gangaram, Niraj K. Jha, Sreejit Chakravarty

Research output: Contribution to journalArticle

1 Scopus citations

Abstract

A digital circuit usually comprises a controller and datapath. The time spent for determining a valid controller behavior to detect a fault usually dominates test generation time. A validation test set is used to verify controller behavior and, hence, it activates various controller behaviors. In this paper, we present a novel methodology wherein the controller behaviors exercised by test sequences in a validation test set are reused for detecting faults in the datapath. A heuristic is used to identify controller behaviors that can justify/propagate pre-computed test vectors/responses of datapath register-transfer level (RTL) modules. Such controller behaviors are said to be compatible with the corresponding precomputed test vectors/responses. The heuristic is fairly accurate, resulting in the detection of a majority of stuck-at faults in the datapath RTL modules. Also, since test generation is performed at the RTL and the controller behavior is predetermined, test generation time is reduced. For microprocessors, if the validation test set consists of instruction sequences then the proposed methodology also generates instruction-level test sequences.

Original languageEnglish (US)
Article number4806115
Pages (from-to)697-708
Number of pages12
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume17
Issue number5
DOIs
StatePublished - May 1 2009

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Keywords

  • Controller/datapath testing
  • Register-transfer level (RTL) testing
  • Validation test sets

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