TY - JOUR
T1 - Fast enhancement of validation test sets for improving the stuck-at fault coverage of RTL circuits
AU - Lingappan, Loganathan
AU - Gangaram, Vijay
AU - Jha, Niraj K.
AU - Chakravarty, Sreejit
N1 - Funding Information:
Manuscript received December 03, 2006; revised November 16, 2007. First published March 27, 2009; current version published April 22, 2009. This work was supported by SRC under Contract 2002-TJ-1039. L. Lingappan and V. Gangaram are with Intel Corporation, Folsom, CA 95630 USA. N. K. Jha is with the Department of Electrical Engineering, Princeton University, Princeton, NJ 08544 USA (e-mail: [email protected]). S. Chakravarty is with LSI Corporation, Milpitas, CA 95035 USA. Digital Object Identifier 10.1109/TVLSI.2009.2013981
PY - 2009/5
Y1 - 2009/5
N2 - A digital circuit usually comprises a controller and datapath. The time spent for determining a valid controller behavior to detect a fault usually dominates test generation time. A validation test set is used to verify controller behavior and, hence, it activates various controller behaviors. In this paper, we present a novel methodology wherein the controller behaviors exercised by test sequences in a validation test set are reused for detecting faults in the datapath. A heuristic is used to identify controller behaviors that can justify/propagate pre-computed test vectors/responses of datapath register-transfer level (RTL) modules. Such controller behaviors are said to be compatible with the corresponding precomputed test vectors/responses. The heuristic is fairly accurate, resulting in the detection of a majority of stuck-at faults in the datapath RTL modules. Also, since test generation is performed at the RTL and the controller behavior is predetermined, test generation time is reduced. For microprocessors, if the validation test set consists of instruction sequences then the proposed methodology also generates instruction-level test sequences.
AB - A digital circuit usually comprises a controller and datapath. The time spent for determining a valid controller behavior to detect a fault usually dominates test generation time. A validation test set is used to verify controller behavior and, hence, it activates various controller behaviors. In this paper, we present a novel methodology wherein the controller behaviors exercised by test sequences in a validation test set are reused for detecting faults in the datapath. A heuristic is used to identify controller behaviors that can justify/propagate pre-computed test vectors/responses of datapath register-transfer level (RTL) modules. Such controller behaviors are said to be compatible with the corresponding precomputed test vectors/responses. The heuristic is fairly accurate, resulting in the detection of a majority of stuck-at faults in the datapath RTL modules. Also, since test generation is performed at the RTL and the controller behavior is predetermined, test generation time is reduced. For microprocessors, if the validation test set consists of instruction sequences then the proposed methodology also generates instruction-level test sequences.
KW - Controller/datapath testing
KW - Register-transfer level (RTL) testing
KW - Validation test sets
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U2 - 10.1109/TVLSI.2009.2013981
DO - 10.1109/TVLSI.2009.2013981
M3 - Article
AN - SCOPUS:67349255821
SN - 1063-8210
VL - 17
SP - 697
EP - 708
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 5
M1 - 4806115
ER -