Fast bit compression and expansion with parallel extract and parallel deposit instructions

Yedidya Hilewitz, Ruby B. Lee

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Scopus citations

Abstract

Current microprocessor instruction set architectures are word oriented, with some subword support. Many important applications, however, can realize substantial performance benefits from bit-oriented instructions. We propose the parallel extract (pex) and parallel deposit (pdep) instructions to accelerate compressing and expanding selections of bits. We show that these instructions can be implemented by the fast inverse butterfly and butterfly network circuits. We evaluate latency and area costs of alternative functional units for implementing subsets of advanced bit manipulation instructions. We show applications exhibiting significant speedup, 3.41× on average over a basic RISC architecture, and 2.48× on average over an instruction set architecture (ISA) that supports extract and deposit instructions.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE 17th International Conference on Application-specific Systems, Architectures and Processors, ASAP 2006
Pages65-70
Number of pages6
DOIs
StatePublished - 2006
EventIEEE 17th International Conference on Application-specific Systems, Architectures and Processors, ASAP 2006 - Steamboat Springs, CO, United States
Duration: Sep 11 2006Sep 13 2006

Publication series

NameProceedings of the International Conference on Application-Specific Systems, Architectures and Processors
ISSN (Print)1063-6862

Other

OtherIEEE 17th International Conference on Application-specific Systems, Architectures and Processors, ASAP 2006
CountryUnited States
CitySteamboat Springs, CO
Period9/11/069/13/06

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Computer Networks and Communications

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