TY - GEN
T1 - Fast bit compression and expansion with parallel extract and parallel deposit instructions
AU - Hilewitz, Yedidya
AU - Lee, Ruby B.
PY - 2006
Y1 - 2006
N2 - Current microprocessor instruction set architectures are word oriented, with some subword support. Many important applications, however, can realize substantial performance benefits from bit-oriented instructions. We propose the parallel extract (pex) and parallel deposit (pdep) instructions to accelerate compressing and expanding selections of bits. We show that these instructions can be implemented by the fast inverse butterfly and butterfly network circuits. We evaluate latency and area costs of alternative functional units for implementing subsets of advanced bit manipulation instructions. We show applications exhibiting significant speedup, 3.41× on average over a basic RISC architecture, and 2.48× on average over an instruction set architecture (ISA) that supports extract and deposit instructions.
AB - Current microprocessor instruction set architectures are word oriented, with some subword support. Many important applications, however, can realize substantial performance benefits from bit-oriented instructions. We propose the parallel extract (pex) and parallel deposit (pdep) instructions to accelerate compressing and expanding selections of bits. We show that these instructions can be implemented by the fast inverse butterfly and butterfly network circuits. We evaluate latency and area costs of alternative functional units for implementing subsets of advanced bit manipulation instructions. We show applications exhibiting significant speedup, 3.41× on average over a basic RISC architecture, and 2.48× on average over an instruction set architecture (ISA) that supports extract and deposit instructions.
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U2 - 10.1109/ASAP.2006.33
DO - 10.1109/ASAP.2006.33
M3 - Conference contribution
AN - SCOPUS:34547443955
SN - 0769526829
SN - 9780769526829
T3 - Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors
SP - 65
EP - 70
BT - Proceedings - IEEE 17th International Conference on Application-specific Systems, Architectures and Processors, ASAP 2006
T2 - IEEE 17th International Conference on Application-specific Systems, Architectures and Processors, ASAP 2006
Y2 - 11 September 2006 through 13 September 2006
ER -