Fabrication of 60-nm transistors on 4-in. wafer using nanoimprint at all lithography levels

Wei Zhang; Stephen Y. Chou

doi:10.1063/1.1600505

Fabrication of 60-nm transistors on 4-in. wafer using nanoimprint at all lithography levels

Wei Zhang
, Stephen Y. Chou

Research output: Contribution to journal › Article › peer-review

111 Scopus citations

Abstract

The fabrication of 60-nm metal-oxide-semiconduictor field-effect transistors was carried out using nanoimprint lithography (NIL). The nanotransistors exhibit excellent operational characteristics across the wafer. The results show a significant advance in nanoimprint development and its application in manufacturing of integrated electrical, optical, chemical, and biological nanocircuits.

Original language	English (US)
Pages (from-to)	1632-1634
Number of pages	3
Journal	Applied Physics Letters
Volume	83
Issue number	8
DOIs	https://doi.org/10.1063/1.1600505
State	Published - Aug 25 2003

All Science Journal Classification (ASJC) codes

Physics and Astronomy (miscellaneous)

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10.1063/1.1600505

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@article{97b70df553b34d088214dd71f228d16b,

title = "Fabrication of 60-nm transistors on 4-in. wafer using nanoimprint at all lithography levels",

abstract = "The fabrication of 60-nm metal-oxide-semiconduictor field-effect transistors was carried out using nanoimprint lithography (NIL). The nanotransistors exhibit excellent operational characteristics across the wafer. The results show a significant advance in nanoimprint development and its application in manufacturing of integrated electrical, optical, chemical, and biological nanocircuits.",

author = "Wei Zhang and Chou, \{Stephen Y.\}",

year = "2003",

month = aug,

day = "25",

doi = "10.1063/1.1600505",

language = "English (US)",

volume = "83",

pages = "1632--1634",

journal = "Applied Physics Letters",

issn = "0003-6951",

publisher = "American Institute of Physics",

number = "8",

}

TY - JOUR

T1 - Fabrication of 60-nm transistors on 4-in. wafer using nanoimprint at all lithography levels

AU - Zhang, Wei

AU - Chou, Stephen Y.

PY - 2003/8/25

Y1 - 2003/8/25

N2 - The fabrication of 60-nm metal-oxide-semiconduictor field-effect transistors was carried out using nanoimprint lithography (NIL). The nanotransistors exhibit excellent operational characteristics across the wafer. The results show a significant advance in nanoimprint development and its application in manufacturing of integrated electrical, optical, chemical, and biological nanocircuits.

AB - The fabrication of 60-nm metal-oxide-semiconduictor field-effect transistors was carried out using nanoimprint lithography (NIL). The nanotransistors exhibit excellent operational characteristics across the wafer. The results show a significant advance in nanoimprint development and its application in manufacturing of integrated electrical, optical, chemical, and biological nanocircuits.

UR - https://www.scopus.com/pages/publications/0041780663

UR - https://www.scopus.com/pages/publications/0041780663#tab=citedBy

U2 - 10.1063/1.1600505

DO - 10.1063/1.1600505

M3 - Article

AN - SCOPUS:0041780663

SN - 0003-6951

VL - 83

SP - 1632

EP - 1634

JO - Applied Physics Letters

JF - Applied Physics Letters

IS - 8

ER -

Fabrication of 60-nm transistors on 4-in. wafer using nanoimprint at all lithography levels

Abstract

All Science Journal Classification (ASJC) codes

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