FAB: Toward flow-aware buffer sharing on programmable switches

Maria Apostolaki, Laurent Vanbever, Manya Ghobadi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Conventional buffer sizing techniques consider an output port with multiple queues in isolation and provide guidelines for the size of the queue. In practice, however, switches consist of several ports that share a buffering chip. Hence, chip manufacturers, such as Broadcom, are left to devise a set of proprietary resource sharing algorithms to allocate buffers across ports. This algorithm dynamically adjusts the buffer size for output queues and directly impacts the packet loss and latency of individual queues. We show that the problem of allocating buffers across ports, although less known, is indeed responsible for fundamental inefficiencies in today's devices. In particular, the per-port buffer allocation is an ad-hoc decision that (at best) depends on the remaining buffer cells on the chip instead of the type of traffic. In this work, we advocate for a flow-aware and device-wide buffer sharing scheme (FAB), which is practical today in programmable devices. We tested FAB on two specific workloads and showed that it can improve the tail flow completion time by an order of magnitude compared to conventional buffer management techniques.

Original languageEnglish (US)
Title of host publicationProceedings of the 2019 Workshop on Buffer Sizing, BS 2019
PublisherAssociation for Computing Machinery
ISBN (Electronic)9781450377454
DOIs
StatePublished - Dec 2 2019
Externally publishedYes
Event2019 Workshop on Buffer Sizing, BS 2019 - Palo Alto, United States
Duration: Dec 2 2019Dec 3 2019

Publication series

NameACM International Conference Proceeding Series

Conference

Conference2019 Workshop on Buffer Sizing, BS 2019
Country/TerritoryUnited States
CityPalo Alto
Period12/2/1912/3/19

All Science Journal Classification (ASJC) codes

  • Software
  • Human-Computer Interaction
  • Computer Vision and Pattern Recognition
  • Computer Networks and Communications

Keywords

  • Buffer management
  • Data center
  • Dynamic buffer threshold
  • Dynamic partitioning
  • Memory utilization
  • Programmable data plane
  • QoS guarantees
  • Resource allocation
  • Shared-memory switch

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