Exploration and evaluation of PLX floating-point instructions and IMplementations for 3D graphics

Xiao Yang, Shamik K. Valia, Michael J. Schulte, Ruby Bei-Loh Lee

Research output: Contribution to journalConference article

Abstract

PLX FP is a floating-point instruction set architecture (ISA) extension to PLX that is designed for fast and efficient 3D graphics processing. In this paper, we explore the implementation and performance of the fundamental functional unit for PLX FP, the floating-point multiply-accumulate (FMAC) functional unit. We present simulation and synthesis results for several implementations with increasingly powerful sets of instructions, to compare area and delay tradeoffs. We also evaluate the performance tradeoffs with examples taken from the 3D graphics processing pipeline.

Original languageEnglish (US)
Pages (from-to)1873-1878
Number of pages6
JournalConference Record - Asilomar Conference on Signals, Systems and Computers
Volume2
StatePublished - Dec 1 2004
EventConference Record of the Thirty-Eighth Asilomar Conference on Signals, Systems and Computers - Pacific Grove, CA, United States
Duration: Nov 7 2004Nov 10 2004

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Computer Networks and Communications

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