Exploration and evaluation of PLX floating-point instructions and IMplementations for 3D graphics

Xiao Yang; Shamik K. Valia; Michael J. Schulte; Ruby B. Lee

Exploration and evaluation of PLX floating-point instructions and IMplementations for 3D graphics

Xiao Yang, Shamik K. Valia, Michael J. Schulte, Ruby B. Lee

Research output: Contribution to journal › Conference article › peer-review

Abstract

PLX FP is a floating-point instruction set architecture (ISA) extension to PLX that is designed for fast and efficient 3D graphics processing. In this paper, we explore the implementation and performance of the fundamental functional unit for PLX FP, the floating-point multiply-accumulate (FMAC) functional unit. We present simulation and synthesis results for several implementations with increasingly powerful sets of instructions, to compare area and delay tradeoffs. We also evaluate the performance tradeoffs with examples taken from the 3D graphics processing pipeline.

Original language	English (US)
Pages (from-to)	1873-1878
Number of pages	6
Journal	Conference Record - Asilomar Conference on Signals, Systems and Computers
Volume	2
State	Published - 2004
Event	Conference Record of the Thirty-Eighth Asilomar Conference on Signals, Systems and Computers - Pacific Grove, CA, United States Duration: Nov 7 2004 → Nov 10 2004

All Science Journal Classification (ASJC) codes

Signal Processing
Computer Networks and Communications

Cite this

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title = "Exploration and evaluation of PLX floating-point instructions and IMplementations for 3D graphics",

abstract = "PLX FP is a floating-point instruction set architecture (ISA) extension to PLX that is designed for fast and efficient 3D graphics processing. In this paper, we explore the implementation and performance of the fundamental functional unit for PLX FP, the floating-point multiply-accumulate (FMAC) functional unit. We present simulation and synthesis results for several implementations with increasingly powerful sets of instructions, to compare area and delay tradeoffs. We also evaluate the performance tradeoffs with examples taken from the 3D graphics processing pipeline.",

author = "Xiao Yang and Valia, {Shamik K.} and Schulte, {Michael J.} and Lee, {Ruby B.}",

year = "2004",

language = "English (US)",

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journal = "Conference Record - Asilomar Conference on Signals, Systems and Computers",

issn = "1058-6393",

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note = "Conference Record of the Thirty-Eighth Asilomar Conference on Signals, Systems and Computers ; Conference date: 07-11-2004 Through 10-11-2004",

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AU - Yang, Xiao

AU - Valia, Shamik K.

AU - Schulte, Michael J.

AU - Lee, Ruby B.

PY - 2004

Y1 - 2004

N2 - PLX FP is a floating-point instruction set architecture (ISA) extension to PLX that is designed for fast and efficient 3D graphics processing. In this paper, we explore the implementation and performance of the fundamental functional unit for PLX FP, the floating-point multiply-accumulate (FMAC) functional unit. We present simulation and synthesis results for several implementations with increasingly powerful sets of instructions, to compare area and delay tradeoffs. We also evaluate the performance tradeoffs with examples taken from the 3D graphics processing pipeline.

AB - PLX FP is a floating-point instruction set architecture (ISA) extension to PLX that is designed for fast and efficient 3D graphics processing. In this paper, we explore the implementation and performance of the fundamental functional unit for PLX FP, the floating-point multiply-accumulate (FMAC) functional unit. We present simulation and synthesis results for several implementations with increasingly powerful sets of instructions, to compare area and delay tradeoffs. We also evaluate the performance tradeoffs with examples taken from the 3D graphics processing pipeline.

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M3 - Conference article

AN - SCOPUS:21644490301

SN - 1058-6393

VL - 2

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JO - Conference Record - Asilomar Conference on Signals, Systems and Computers

JF - Conference Record - Asilomar Conference on Signals, Systems and Computers

T2 - Conference Record of the Thirty-Eighth Asilomar Conference on Signals, Systems and Computers

Y2 - 7 November 2004 through 10 November 2004

ER -

Exploration and evaluation of PLX floating-point instructions and IMplementations for 3D graphics

Abstract

All Science Journal Classification (ASJC) codes

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