Exploiting operation level parallelism through dynamically reconfigurable datapaths

Keyphrases

• Application Specific Integrated Circuits 100%
• Bit Level 33%
• Circuit Solutions 66%
• Coders 66%
• Complete Case 33%
• Coprocessor 100%
• Design Environment 33%
• Dynamically Configurable 33%
• Dynamically Reconfigurable 100%
• Energy Overhead 33%
• Engineering Cost 33%
• Field Programmable Gate Array 33%
• Function Reconfiguration 33%
• Function Unit 33%
• General Purpose Processor 33%
• Hardwired 100%
• High Cost 33%
• High-speed Applications 33%
• Hybrid Solutions 33%
• Logic Block 33%
• Mask Cost 33%
• Medium Volume 33%
• MPEG-2 33%
• Non-recurring Engineering 33%
• Operation Level 100%
• Parallelization 100%
• Performance Overhead 33%
• Product Volume 33%
• Programmability 33%
• Programmable Platform 66%
• Reconfigurable Datapath 100%
• Reconfigurable Interconnection 33%
• Single Instruction 33%
• VLIW Processor 66%
• Word-level 33%

Computer Science

• Application Performance 33%
• Application Specific Integrated Circuit 100%
• Case Study 33%
• Coder 66%
• Coprocessor 100%
• Datapath 100%
• Field Programmable Gate Array 33%
• General Purpose Processor 33%
• Hybrid Solution 33%
• Level Parallelism 100%
• Loop Kernel 33%
• MPEG 33%
• Programmability 33%
• Single Instruction 33%
• VLIW Processor 66%