Exploiting operation level parallelism through dynamically reconfigurable datapaths

Zhining Huang, Sharad Malik

Research output: Chapter in Book/Report/Conference proceedingConference contribution

23 Scopus citations

Abstract

Increasing non-recurring engineering (NRE) and mask costs are making it harder to turn to hardwired Application Specific Integrated Circuit (ASIC) solutions for high performance applications. The volume required to amortize these high costs has been increasing, making it increasingly expensive to afford ASIC solutions for medium volume products. This has led to designers seeking programmable solutions of varying sorts using these so-called programmable platforms. These programmable platforms span a large range from bit-level programmable Field Programmable Gate Arrays (FPGAs), to word-level programmable application-specific, and in some cases even general-purpose processors. The programmability comes with a power and performance overhead. Attempts to reduce this overhead typically involve making some core hardwired ASIC like logic blocks accessible to the programmable elements. This paper presents one such hybrid solution in this space - a relatively simple processor with a dynamically reconfigurable datapath acting as an accelerating co-processor. This datapath consists of hardwired function units and reconfigurable interconnect. We present a methodology for the design of these solutions and illustrate it with two complete case studies: an MPEG 2 coder, and a GSM coder, to show how significant speedups can be obtained using relatively little hardware. The co-processor can be viewed as a VLIW processor with a single instruction per kernel loop. We compare the efficiency of exploiting the operation level parallelism using classic VLIW processors and this proposed class of dynamically configurable co-processors. This work is part of the MESCAL project, which is geared towards developing design environments for the development of application specific platforms.

Original languageEnglish (US)
Title of host publicationProceedings of the 39th Annual Design Automation Conference, DAC'02
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages337-342
Number of pages6
ISBN (Print)1581134614
DOIs
StatePublished - 2002
Event39th Design Automation Conference - New Orleans, LA, United States
Duration: Jun 10 2002Jun 14 2002

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X

Conference

Conference39th Design Automation Conference
CountryUnited States
CityNew Orleans, LA
Period6/10/026/14/02

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Control and Systems Engineering

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    Huang, Z., & Malik, S. (2002). Exploiting operation level parallelism through dynamically reconfigurable datapaths. In Proceedings of the 39th Annual Design Automation Conference, DAC'02 (pp. 337-342). (Proceedings - Design Automation Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/513918.514006