Exploiting Multicycle False Paths in the Performance Optimization of Sequential Logic Circuits

Pranav Ashar, Sujit Dey, Sharad Malik

Research output: Contribution to journalArticle

11 Scopus citations

Abstract

This paper addresses the performance optimization problem for sequential logic circuits. It is shown how the notion of false paths, traditionally defined for combinational logic circuits, can be extended to the sequential context by considering the operation of the circuit over multiple clock-cycles. These multicycle false paths can be removed from the circuit using techniques similar to those proposed for combinational logic circuits. This observation offers new techniques to improve the performance of sequential logic circuits. An implementation of an algorithm that uses these ideas shows significant performance improvement on some typical benchmark circuits at a modest area overhead.

Original languageEnglish (US)
Pages (from-to)1067-1075
Number of pages9
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume14
Issue number9
DOIs
StatePublished - Sep 1995

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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