This paper addresses the performance optimization problem for sequential circuits. It is shown how the notion of false paths, traditionally defined for combinational logic circuits, can be extended to the sequential context by considering the operation of the circuit over multiple clock-cycles. Multicycle false paths can be removed from the circuit using techniques similar to those proposed for combinational logic circuits. This observation offers new techniques to improve the performance of sequential logic circuits. A preliminary implementation of an algorithm that uses these ideas shows significant performance improvement on some typical benchmark circuits at a very modest area overhead.