Exploiting multi-cycle false paths in the performance optimization of sequential circuits

Pranav Ashar, Sujit Dey, Sharad Malik

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Scopus citations

Abstract

This paper addresses the performance optimization problem for sequential circuits. It is shown how the notion of false paths, traditionally defined for combinational logic circuits, can be extended to the sequential context by considering the operation of the circuit over multiple clock-cycles. Multicycle false paths can be removed from the circuit using techniques similar to those proposed for combinational logic circuits. This observation offers new techniques to improve the performance of sequential logic circuits. A preliminary implementation of an algorithm that uses these ideas shows significant performance improvement on some typical benchmark circuits at a very modest area overhead.

Original languageEnglish (US)
Title of host publicationIEEE/ACM International Conference on Computer-Aided Design
PublisherPubl by IEEE
Pages510-517
Number of pages8
ISBN (Print)0818630108
StatePublished - Dec 1 1992
Externally publishedYes
EventIEEE/ACM International Conference on Computer-Aided Design - ICCAD '92 - Santa Clara, CA, USA
Duration: Nov 8 1992Nov 12 1992

Publication series

NameIEEE/ACM International Conference on Computer-Aided Design

Other

OtherIEEE/ACM International Conference on Computer-Aided Design - ICCAD '92
CitySanta Clara, CA, USA
Period11/8/9211/12/92

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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  • Cite this

    Ashar, P., Dey, S., & Malik, S. (1992). Exploiting multi-cycle false paths in the performance optimization of sequential circuits. In IEEE/ACM International Conference on Computer-Aided Design (pp. 510-517). (IEEE/ACM International Conference on Computer-Aided Design). Publ by IEEE.