TY - GEN
T1 - Exploiting circuit reconvergence through static learning in CNF SAT solvers
AU - Yu, Yinlei
AU - Brien, Cameron
AU - Malik, Sharad
PY - 2008
Y1 - 2008
N2 - Most contemporary SAT solvers use a Conjunctive-Normal-Form (CNF) representation for logic functions due to the availability of efficient algorithms for this form, such as deduction through unit propagation and conflict driven learning using clause resolution. The use of CNF generally entails transformation to this form from other representations such as logic circuits [23]. However, this transformation results in loss of information such as direction of signal flow and observability of signals at circuit outputs [12][13]. This has prompted the development of various circuit-based solvers [2][14][17][22], hybrid CNF+circuit-based solvers[13], as well as augmented CNF solvers [12]. Having the circuit available provides for additional capabilities at a cost, and thus requires careful analysis to determine the viability of each approach. This paper highlights one specific capability provided by a circuit: the ability to consider reconvergent paths in unit propagation. Unit propagation is the workhorse of contemporary SAT solvers, thus any improvement to this has significant practical potential. We first demonstrate that the Tseitin circuit-to-CNF transformation limits back-ward unit propagation and how additional implications can be derived when unit propagation across multiple paths is considered. Next, we show how these implications can be exploited by statically learning clauses during circuit pre-processing. The results of the practical implementation of these algorithms show that the static learning can provide significant speed-up on several classes of bench-mark circuits. Finally, we discuss how this work compares with other circuit-based approaches, especially those arising from the automatic-test-pattern-generation (ATPG) community (e.g. recursive learning) and circuit and non-circuit based pre-processors.
AB - Most contemporary SAT solvers use a Conjunctive-Normal-Form (CNF) representation for logic functions due to the availability of efficient algorithms for this form, such as deduction through unit propagation and conflict driven learning using clause resolution. The use of CNF generally entails transformation to this form from other representations such as logic circuits [23]. However, this transformation results in loss of information such as direction of signal flow and observability of signals at circuit outputs [12][13]. This has prompted the development of various circuit-based solvers [2][14][17][22], hybrid CNF+circuit-based solvers[13], as well as augmented CNF solvers [12]. Having the circuit available provides for additional capabilities at a cost, and thus requires careful analysis to determine the viability of each approach. This paper highlights one specific capability provided by a circuit: the ability to consider reconvergent paths in unit propagation. Unit propagation is the workhorse of contemporary SAT solvers, thus any improvement to this has significant practical potential. We first demonstrate that the Tseitin circuit-to-CNF transformation limits back-ward unit propagation and how additional implications can be derived when unit propagation across multiple paths is considered. Next, we show how these implications can be exploited by statically learning clauses during circuit pre-processing. The results of the practical implementation of these algorithms show that the static learning can provide significant speed-up on several classes of bench-mark circuits. Finally, we discuss how this work compares with other circuit-based approaches, especially those arising from the automatic-test-pattern-generation (ATPG) community (e.g. recursive learning) and circuit and non-circuit based pre-processors.
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U2 - 10.1109/VLSI.2008.90
DO - 10.1109/VLSI.2008.90
M3 - Conference contribution
AN - SCOPUS:47649087619
SN - 0769530834
SN - 9780769530833
T3 - Proceedings of the IEEE International Frequency Control Symposium and Exposition
SP - 461
EP - 468
BT - Proceedings - 21st International Conference on VLSI Design, VLSI DESIGN 2008
T2 - 21st International Conference on VLSI Design, VLSI DESIGN 2008
Y2 - 4 January 2008 through 8 January 2008
ER -