Event Suppression: Improving the Efficiency of Timing Simulation for Synchronous Digital Circuits

Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang

Research output: Contribution to journalArticlepeer-review

10 Scopus citations

Abstract

Timing simulation is a widely used method to verify the timing behavior of a design. In a synchronous digital system the timing property that needs to be verified is that there is no event at the outputs of the combinational parts of the circuit at or after time τ, the clock period. In this paper we first show that conventional timing simulation applied to this problem has exponential complexity. Next we demonstrate that for this problem a complete history of circuit activity before time τ is not needed. We exploit this observation and present an event suppression method that potentially leads to an exponential reduction in the number of events that need to be processed during simulation. This is backed by encouraging experimental results.

Original languageEnglish (US)
Pages (from-to)814-822
Number of pages9
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume13
Issue number6
DOIs
StatePublished - Jan 1 1994

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Event Suppression: Improving the Efficiency of Timing Simulation for Synchronous Digital Circuits'. Together they form a unique fingerprint.

Cite this