Abstract

Multicomputers can be effectively used for interactive graphics rendering only if there are mechanisms available to rapidly composite and transfer images to an external display device. One method for achieving the necessary bandwidth for this operation is to provide multiple high-bandwidth ports into a frame buffer. In this paper, we evaluate the design space of a multi-port frame buffer design for the Intel Paragon mesh routing network. We use an instrumented rendering system to capture the graphics operations needed for rendering a number of three-dimensional scenes; we then use those workloads as input to test programs running on the Paragon to estimate the performance of our hardware. Our experiments consider three major design questions: how many network ports the frame buffer needs, whether Z-Buffering should be done in hardware on the frame buffer or in software on the computing nodes, and whether the design alternatives are scalable.

Original languageEnglish (US)
Pages96-105
Number of pages10
DOIs
StatePublished - 1995
EventProceedings of the 22nd Annual International Symposium on Computer Architecture - Santa Margherita Ligure, Italy
Duration: Jun 22 1995Jun 24 1995

Other

OtherProceedings of the 22nd Annual International Symposium on Computer Architecture
CitySanta Margherita Ligure, Italy
Period6/22/956/24/95

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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    Stoll, G., Wei, B., Clark, D., Felten, E. W., & Li, K. (1995). Evaluating multi-port frame buffer designs for a mesh-connected multicomputer. 96-105. Paper presented at Proceedings of the 22nd Annual International Symposium on Computer Architecture, Santa Margherita Ligure, Italy, . https://doi.org/10.1145/225830.224043