Evaluating instruction set extensions for fast arithmetic on binary finite fields

A. Murat Fiskiran, Ruby B. Lee

Research output: Contribution to journalConference articlepeer-review

12 Scopus citations


The evaluation of arithmetic instructions for processors with wider wordsizes and multiple-issue execution is reported. The effects of varying the number of functional units and load/store pipes are considered. It is demonstrated that the combination of microarchitecture and new instructions provides speedups up to 22.4×for ECC point multiplication. It is observed that if a bit-level reverse instruction is included in the instruction set, the size of the multiplier can be reduced by half without significant performance degradation.

Original languageEnglish (US)
Pages (from-to)125-136
Number of pages12
JournalProceedings of the International Conference on Application-Specific Systems, Architectures and Processors
StatePublished - 2004
EventProceedings - 15th IEEE International Conference on Applications-Specific Systems, Architectures and Processors - Galveston, TX, United States
Duration: Sep 27 2004Sep 29 2004

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Computer Networks and Communications


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