Technological scaling and system-complexity scaling have dramatically increased the prevalence of hardware faults, to the point where traditional approaches based on design margining are becoming un-viable. The challenges are exacerbated in embedded sensing applications due to constraints on system resources (energy, area). Given the importance of classification functions in such applications, this paper presents an architecture for overcoming faults within a classification processor. The approach employs machine learning for modeling not only complex sensor signals but also error manifestations due to hardware faults. Adaptive boosting is exploited in the architecture for performing iterative data-driven training. This enables the effects of faults in preceding iterations to be modeled and overcome during subsequent iterations. We demonstrate a system integrating the proposed classifier, capable of training its model entirely within the architecture by generating estimated training labels. FPGA experiments show that high fault rates (affecting >3% of all circuit nodes) occurring on >80% of the hardware can be overcome, restoring system performance to fault-free levels.