Energy Characterization of a Tiled Architecture Processor with On-Chip Networks

Jason Sungtae Kim, Michael Bedford Taylor, Jason Miller, David Wentzlaff

Research output: Contribution to journalConference article

96 Scopus citations

Abstract

Tiled architectures provide a paradigm for designers to turn silicon resources into processors with burgeoning quantities of programmable functional units and memories. The architecture has a dual responsibility: first, it must expose these resources in a way that is programmable. Second, it needs to manage the power associated with such resources. We present the power management facilities of the 16-tile Raw microprocessor. This design selectively turns on and off 48 SRAM macros, 96 functional unit clusters, 32 fetch units, and over 250 unique processor pipeline stages, all according to the needs of the computation and environment at hand.

Original languageEnglish (US)
Pages (from-to)424-427
Number of pages4
JournalProceedings of the International Symposium on Low Power Electronics and Design
StatePublished - Dec 1 2003
EventProceedings of the 2003 International Symposium on Low Power Electronics and Design, (ISLPED'03) - Seoul, Korea, Republic of
Duration: Aug 25 2003Aug 27 2003

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Keywords

  • Power
  • Raw Microprocessor
  • Scalar Operand Network
  • Tile

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