Energy Characterization of a Tiled Architecture Processor with On-Chip Networks

Jason Sungtae Kim; Michael Bedford Taylor; Jason Miller; David Wentzlaff

Energy Characterization of a Tiled Architecture Processor with On-Chip Networks

Jason Sungtae Kim, Michael Bedford Taylor, Jason Miller, David Wentzlaff

Research output: Contribution to journal › Conference article › peer-review

Abstract

Tiled architectures provide a paradigm for designers to turn silicon resources into processors with burgeoning quantities of programmable functional units and memories. The architecture has a dual responsibility: first, it must expose these resources in a way that is programmable. Second, it needs to manage the power associated with such resources. We present the power management facilities of the 16-tile Raw microprocessor. This design selectively turns on and off 48 SRAM macros, 96 functional unit clusters, 32 fetch units, and over 250 unique processor pipeline stages, all according to the needs of the computation and environment at hand.

Original language	English (US)
Pages (from-to)	424-427
Number of pages	4
Journal	Proceedings of the International Symposium on Low Power Electronics and Design
State	Published - Dec 1 2003
Event	Proceedings of the 2003 International Symposium on Low Power Electronics and Design, (ISLPED'03) - Seoul, Korea, Republic of Duration: Aug 25 2003 → Aug 27 2003

All Science Journal Classification (ASJC) codes

General Engineering

Keywords

Power
Raw Microprocessor
Scalar Operand Network
Tile

Cite this

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title = "Energy Characterization of a Tiled Architecture Processor with On-Chip Networks",

abstract = "Tiled architectures provide a paradigm for designers to turn silicon resources into processors with burgeoning quantities of programmable functional units and memories. The architecture has a dual responsibility: first, it must expose these resources in a way that is programmable. Second, it needs to manage the power associated with such resources. We present the power management facilities of the 16-tile Raw microprocessor. This design selectively turns on and off 48 SRAM macros, 96 functional unit clusters, 32 fetch units, and over 250 unique processor pipeline stages, all according to the needs of the computation and environment at hand.",

keywords = "Power, Raw Microprocessor, Scalar Operand Network, Tile",

author = "Kim, {Jason Sungtae} and Taylor, {Michael Bedford} and Jason Miller and David Wentzlaff",

year = "2003",

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day = "1",

language = "English (US)",

pages = "424--427",

journal = "Proceedings of the International Symposium on Low Power Electronics and Design",

issn = "1533-4678",

note = "Proceedings of the 2003 International Symposium on Low Power Electronics and Design, (ISLPED'03) ; Conference date: 25-08-2003 Through 27-08-2003",

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TY - JOUR

T1 - Energy Characterization of a Tiled Architecture Processor with On-Chip Networks

AU - Kim, Jason Sungtae

AU - Taylor, Michael Bedford

AU - Miller, Jason

AU - Wentzlaff, David

PY - 2003/12/1

Y1 - 2003/12/1

N2 - Tiled architectures provide a paradigm for designers to turn silicon resources into processors with burgeoning quantities of programmable functional units and memories. The architecture has a dual responsibility: first, it must expose these resources in a way that is programmable. Second, it needs to manage the power associated with such resources. We present the power management facilities of the 16-tile Raw microprocessor. This design selectively turns on and off 48 SRAM macros, 96 functional unit clusters, 32 fetch units, and over 250 unique processor pipeline stages, all according to the needs of the computation and environment at hand.

AB - Tiled architectures provide a paradigm for designers to turn silicon resources into processors with burgeoning quantities of programmable functional units and memories. The architecture has a dual responsibility: first, it must expose these resources in a way that is programmable. Second, it needs to manage the power associated with such resources. We present the power management facilities of the 16-tile Raw microprocessor. This design selectively turns on and off 48 SRAM macros, 96 functional unit clusters, 32 fetch units, and over 250 unique processor pipeline stages, all according to the needs of the computation and environment at hand.

KW - Power

KW - Raw Microprocessor

KW - Scalar Operand Network

KW - Tile

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UR - http://www.scopus.com/inward/citedby.url?scp=1542299262&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:1542299262

SN - 1533-4678

SP - 424

EP - 427

JO - Proceedings of the International Symposium on Low Power Electronics and Design

JF - Proceedings of the International Symposium on Low Power Electronics and Design

T2 - Proceedings of the 2003 International Symposium on Low Power Electronics and Design, (ISLPED'03)

Y2 - 25 August 2003 through 27 August 2003

ER -

Energy Characterization of a Tiled Architecture Processor with On-Chip Networks

Abstract

All Science Journal Classification (ASJC) codes

Keywords

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