TY - GEN
T1 - Enabling programmable transport protocols in high-speed NICs
AU - Arashloo, Mina Tahmasbi
AU - Lavrov, Alexey
AU - Ghobadi, Manya
AU - Rexford, Jennifer
AU - Walker, David
AU - Wentzlaff, David
N1 - Publisher Copyright:
© Proc. of the 17th USENIX Symposium on Networked Systems Design and Impl., NSDI 2020. All rights reserved.
PY - 2020
Y1 - 2020
N2 - Data-center network stacks are moving into hardware to achieve 100 Gbps data rates and beyond at low latency and low CPU utilization. However, hardwiring the network stack in the NIC would stifle innovation in transport protocols. In this paper, we enable programmable transport protocols in high-speed NICs by designing Tonic, a flexible hardware architecture for transport logic. At 100 Gbps, transport protocols must generate a data segment every few nanoseconds using only a few kilobits of per-flow state on the NIC. By identifying common patterns across transport logic of different transport protocols, we design an efficient hardware “template” for transport logic that satisfies these constraints while being programmable with a simple API. Experiments with our FPGA-based prototype show that Tonic can support the transport logic of a wide range of protocols and meet timing for 100 Gbps of back-to-back 128-byte packets. That is, every 10 ns, our prototype generates the address of a data segment for one of more than a thousand active flows for a downstream DMA pipeline to fetch and transmit a packet.
AB - Data-center network stacks are moving into hardware to achieve 100 Gbps data rates and beyond at low latency and low CPU utilization. However, hardwiring the network stack in the NIC would stifle innovation in transport protocols. In this paper, we enable programmable transport protocols in high-speed NICs by designing Tonic, a flexible hardware architecture for transport logic. At 100 Gbps, transport protocols must generate a data segment every few nanoseconds using only a few kilobits of per-flow state on the NIC. By identifying common patterns across transport logic of different transport protocols, we design an efficient hardware “template” for transport logic that satisfies these constraints while being programmable with a simple API. Experiments with our FPGA-based prototype show that Tonic can support the transport logic of a wide range of protocols and meet timing for 100 Gbps of back-to-back 128-byte packets. That is, every 10 ns, our prototype generates the address of a data segment for one of more than a thousand active flows for a downstream DMA pipeline to fetch and transmit a packet.
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M3 - Conference contribution
AN - SCOPUS:85086822826
T3 - Proceedings of the 17th USENIX Symposium on Networked Systems Design and Implementation, NSDI 2020
SP - 93
EP - 109
BT - Proceedings of the 17th USENIX Symposium on Networked Systems Design and Implementation, NSDI 2020
PB - USENIX Association
T2 - 17th USENIX Symposium on Networked Systems Design and Implementation, NSDI 2020
Y2 - 25 February 2020 through 27 February 2020
ER -