TY - GEN
T1 - EMISSARY
T2 - 50th Annual International Symposium on Computer Architecture, ISCA 2023
AU - Nagendra, Nayana Prasad
AU - Patel, Atmn
AU - Stark, Jared
AU - Godala, Bhargav Reddy
AU - Kanev, Svilen
AU - Pokam, Gilles A.
AU - August, David I.
AU - Chaturvedi, Ishita
AU - Moseley, Tipp
AU - Campanoni, Simone
N1 - Publisher Copyright:
© 2023 Institute of Electrical and Electronics Engineers Inc.. All rights reserved.
PY - 2023/6/17
Y1 - 2023/6/17
N2 - For decades, architects have designed cache replacement policies to reduce cache misses. Since not all cache misses affect processor performance equally, researchers have also proposed cache replacement policies focused on reducing the total miss cost rather than the total miss count. However, all prior cost-aware replacement policies have been proposed specifically f or d ata caching and are either inappropriate or unnecessarily complex for instruction caching. This paper presents EMISSARY, the first cost-aware cache replacement family of policies specifically designed for instruction caching. Observing that modern architectures entirely tolerate many instruction cache misses, EMISSARY resists evicting those cache lines whose misses cause costly decode starvations. In the context of a modern processor with fetch-directed instruction prefetching and other aggressive front-end features, EMISSARY applied to L2 cache instructions delivers an impressive 3.24% geomean speedup (up to 23.7%) and a geomean energy savings of 2.1% (up to 17.7%) when evaluated on widely used server applications with large code footprints. This speedup is 21.6% of the total speedup obtained by an unrealizable L2 cache with a zero-cycle miss latency for all capacity and conflict instruction misses.
AB - For decades, architects have designed cache replacement policies to reduce cache misses. Since not all cache misses affect processor performance equally, researchers have also proposed cache replacement policies focused on reducing the total miss cost rather than the total miss count. However, all prior cost-aware replacement policies have been proposed specifically f or d ata caching and are either inappropriate or unnecessarily complex for instruction caching. This paper presents EMISSARY, the first cost-aware cache replacement family of policies specifically designed for instruction caching. Observing that modern architectures entirely tolerate many instruction cache misses, EMISSARY resists evicting those cache lines whose misses cause costly decode starvations. In the context of a modern processor with fetch-directed instruction prefetching and other aggressive front-end features, EMISSARY applied to L2 cache instructions delivers an impressive 3.24% geomean speedup (up to 23.7%) and a geomean energy savings of 2.1% (up to 17.7%) when evaluated on widely used server applications with large code footprints. This speedup is 21.6% of the total speedup obtained by an unrealizable L2 cache with a zero-cycle miss latency for all capacity and conflict instruction misses.
KW - Cache Microarchitecture
KW - Cache Replacement Policy
KW - Cost-Aware Replacement Policy
KW - Instruction Caching
UR - http://www.scopus.com/inward/record.url?scp=85168880274&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85168880274&partnerID=8YFLogxK
U2 - 10.1145/3579371.3589097
DO - 10.1145/3579371.3589097
M3 - Conference contribution
AN - SCOPUS:85168880274
T3 - Proceedings - International Symposium on Computer Architecture
SP - 869
EP - 881
BT - ISCA 2023 - Proceedings of the 2023 50th Annual International Symposium on Computer Architecture
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 17 June 2023 through 21 June 2023
ER -