The complexity of a microprocessor, with its large number of embedded structures, presents a particular challenge to any single-chip testing methodology. The authors compare test generation and test application methodologies in an effort to identify the more efficient methodologies for microprocessor structural testing. It is demonstrated that RISC architectures facilitate structural testing by means of the normal program execution. Experimental results on logic circuits and memory units illustrate the efficiency of the proposed methodology for both test vector generation and test application for an industrial RISC microprocessor.
|Original language||English (US)|
|Title of host publication||Unknown Host Publication Title|
|Number of pages||4|
|State||Published - Dec 1 1986|
All Science Journal Classification (ASJC) codes