EFFICIENT TESTING OF RISC MICROPROCESSORS.

Jim Tsen Gong Hsu, Ruby Bei-Loh Lee, Gregory D. Burroughs

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

The complexity of a microprocessor, with its large number of embedded structures, presents a particular challenge to any single-chip testing methodology. The authors compare test generation and test application methodologies in an effort to identify the more efficient methodologies for microprocessor structural testing. It is demonstrated that RISC architectures facilitate structural testing by means of the normal program execution. Experimental results on logic circuits and memory units illustrate the efficiency of the proposed methodology for both test vector generation and test application for an industrial RISC microprocessor.

Original languageEnglish (US)
Title of host publicationUnknown Host Publication Title
PublisherIEEE
Pages15-18
Number of pages4
ISBN (Print)0818607440
StatePublished - Dec 1 1986
Externally publishedYes

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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  • Cite this

    Hsu, J. T. G., Lee, R. B-L., & Burroughs, G. D. (1986). EFFICIENT TESTING OF RISC MICROPROCESSORS. In Unknown Host Publication Title (pp. 15-18). IEEE.