Efficient techniques for timing correction

C. Leonard Berman, David J. Hathaway, Andrea Suzanne LaPaugh, Louise H. Trevillyan

Research output: Contribution to journalArticle

9 Scopus citations

Abstract

Three computationally efficient methods (frontier motion, Shannon expansion, and Boolean distribution) for restructuring logic which fails to meet timing specifications are described. These techniques appear, at first glance, to be unrelated; however, it is shown that there is a deep underlying connection among them. These methods are used in IBM's LSS. The results of experiments that demonstrate that timing correction can be effectively performed on industrial examples in the context of a compilerlike logic synthesis system are reported.

Original languageEnglish (US)
Pages (from-to)415-419
Number of pages5
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume1
StatePublished - Dec 1 1990
Externally publishedYes

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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    Berman, C. L., Hathaway, D. J., LaPaugh, A. S., & Trevillyan, L. H. (1990). Efficient techniques for timing correction. Proceedings - IEEE International Symposium on Circuits and Systems, 1, 415-419.