Efficient techniques for timing correction

C. Leonard Berman, David J. Hathaway, Andrea S. LaPaugh, Louise H. Trevillyan

Research output: Contribution to journalConference articlepeer-review

10 Scopus citations


Three computationally efficient methods (frontier motion, Shannon expansion, and Boolean distribution) for restructuring logic which fails to meet timing specifications are described. These techniques appear, at first glance, to be unrelated; however, it is shown that there is a deep underlying connection among them. These methods are used in IBM's LSS. The results of experiments that demonstrate that timing correction can be effectively performed on industrial examples in the context of a compilerlike logic synthesis system are reported.

Original languageEnglish (US)
Pages (from-to)415-419
Number of pages5
JournalProceedings - IEEE International Symposium on Circuits and Systems
StatePublished - 1990
Event1990 IEEE International Symposium on Circuits and Systems Part 4 (of 4) - New Orleans, LA, USA
Duration: May 1 1990May 3 1990

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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