Three computationally efficient methods (frontier motion, Shannon expansion, and Boolean distribution) for restructuring logic which fails to meet timing specifications are described. These techniques appear, at first glance, to be unrelated; however, it is shown that there is a deep underlying connection among them. These methods are used in IBM's LSS. The results of experiments that demonstrate that timing correction can be effectively performed on industrial examples in the context of a compilerlike logic synthesis system are reported.
|Original language||English (US)|
|Number of pages||5|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|State||Published - Dec 1 1990|
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials