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Effects on VLSI Yield of Doubly-Stochastic Impurity Distributions
Paul R. Prucnal
, Howard C. Card
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peer-review
2
Scopus citations
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Keyphrases
Device Yield
100%
Impurity Distribution
100%
Very Large Scale Integration
100%
Parity Check
100%
Doubly Stochastic
100%
Chip Yield
83%
Device Parameters
33%
Large chips
33%
Implantation Parameters
33%
Device Dimensions
33%
Threshold Effect
16%
Reliable System
16%
Device Sizing
16%
Specific Parameters
16%
16-bit
16%
Small Devices
16%
Bipolar Transistor
16%
Ion Implantation
16%
Yield Limit
16%
Yield Decline
16%
Stochastic Effects
16%
Number of Bits
16%
System Performance
16%
Impurities
16%
Device Behavior
16%
Base Region
16%
Example Calculation
16%
Engineering
VLSI Circuits
100%
Parity Bit
100%
Ion Implantation
50%
Base Region
50%
Bipolar Transistor
50%
Great Number
50%
Device Behavior
50%
Systems Performance
50%
Material Science
Bipolar Transistor
100%
Ion Implantation
100%
Pharmacology, Toxicology and Pharmaceutical Science
Base
100%