Effects on VLSI Yield of Doubly-Stochastic Impurity Distributions

An expression is derived for the doublystochastic distribution of the number of impurities in the base region of a bipolar transistor; the distribution results from uncertainty in ion implantation parameters. Expressions are derived for device yield, and VLSI (very large scale integration) chip yield with an N-bit parity check. These derivations can be extended to other devices in a straightforward manner. As an example, calculations have been performed using specific parameters, which have led to the following observations: 1. The doubly stochastic effect is most sensitive to uncertainty in the straggle (standard deviation) of the emitter impurity distribution. 2. Uncertainty of the order of 5% in an implantation parameter causes substantial broadening of the distribution of impurities, for the case considered. 3. Device yield decreases rapidly for dimensions less than a welldefined threshold (≈ 0.75 μm for the case considered). 4. Chip yield, without a parity check, exhibits a threshold effect at device yield = 1-1/N chip. (N chip ≡number of devices per chip.) The device yield must exceed this threshold to produce large chip yields. 5. The use of a parity check reduces the device yield threshold to 1-10/N Chip. Use of fewer bits per parity check reduces the threshold further. 6. For the example considered, the minimum device dimensions for large chip yields is of the order of 1 to 1.5 μm, using a 16-bit parity check. The minimum device size for reliable system performance for other cases will depend upon specific device parameters. However, it is apparent that chip yield is extremely sensitive to individual device yield, and that it decreases with increasing uncertainty in device parameters, smaller device dimensions, greater number of devices per chip, larger number of bits per parity check, and with smaller allowed ranges of tolerable device behavior.