Effects of film morphology and gate dielectric surface preparation on the electrical characteristics of organic-vapor-phase-deposited pentacene thin-film transistors

Organic vapor phase deposition was used to grow polycrystalline pentacene channel thin-film transistors. Substrate temperature, chamber pressure during film deposition, and growth rate were used to vary the crystalline grain size of pentacene films on O₂-plasma treated SiO₂ from 0.2 to 5 μm, leading to room-temperature saturation regime field-effect hole mobilities (μ_eff) from 0.05±0.02 to 0.5±0.1cm ²/Vs, respectively. Surface treatment of SiO₂ with octadecyltrichlorosilane (OTS) prior to pentacene deposition resulted in μ_eff≤1.6cm²/Vs, and drain current on/off ratios of ≤10⁸ at room temperature, while dramatically reducing the average grain size. X-ray diffraction studies indicate that the OTS treatment decreases the order of the molecular stacks. This suggests an increased density of flat-lying molecules, accompanying the improvement of the hole mobility at the pentacene/OTS interface.