## Abstract

In this paper, the problem of design for testability of gate-level array dividers is investigated. Both nonrestoring and restoring array dividers are considered. The single stuck-at fault model is used for these designs. Two C-testable designs are given for the nonrestoring array divider. The first design is C-testable with only eight vectors. The additional hardware required to obtain C-testability for an n x n nonrestoring array divider consists only of n — 1 two-input gates and one control input. In the second design we assume that a particular logic implementation is used for the full adder. A full adder happens to be a part of every cell in the array. Such a design does not, surprisingly, require any extra circuitry or control inputs, and is C-testable with six vectors. In other words, the basic array structure itself is C-testable. We also present two easily testable designs for the restoring array divider. The first n × n array design is shown to be linearly testable with 2n + 8 vectors. The extra hardware required consists of n xor gates and one control input. In the second design, a particular logic implementation is used for realizing the sum and carry functions in each cell. This makes the design C-testable with only six vectors. The extra circuitry required for this design is the same as that required for the first one.

Original language | English (US) |
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Pages (from-to) | 114-123 |

Number of pages | 10 |

Journal | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |

Volume | 12 |

Issue number | 1 |

DOIs | |

State | Published - Jan 1993 |

## All Science Journal Classification (ASJC) codes

- Software
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering