TY - JOUR

T1 - Easily Testable Gate-Level and DCVS Multipliers

AU - Takach, Andres R.

AU - Jha, Niraj K.

N1 - Funding Information:
Manuscript received February 14, 1990. This work was supported in part by the National Science Foundation under Grant MIP-8815674.T his paper was recommended by Associate Editor S. C. Seth. The authors are-with the Department of Electrical Engineering, Princeton University, Princeton, NJ 08544. IEEE Log Number 9143302.

PY - 1991/7

Y1 - 1991/7

N2 - In this paper some C-testable designs of a carry-save parallel multiplier are presented. Results are given for both the gate-level implementation and the differential cascode voltage switch (DCVS) implementation. DCVS circuits are dynamic CMOS circuits which have the advantage of being protected against test set invalidation due to circuit delays. In the first gate-level design we assume that the full-adders have any arbitrary, irredundant logic implementation. Such a design is C-testable with only 9 test vectors, which detect all single stuck-at faults. For a specific logic implementation of the full-adders, another design is shown to be C-testable with only 6 test vectors. The DCVS design is also C-testable with only 6 test vectors, which detect all detectable stuck-at, stuck-on, and stuck-open faults in the circuit. The hardware for the first gate-level design for an n x n multiplier consists of n(n - 1) full-adders, a summand generator consisting of n22-input and gates, as well as 6 extra 2- or 3-input gates and n extra 2-input ex-or gates to enhance the controllability of the circuit. Two additional controllable inputs are also required for this gate-level design. In the second gate-level design for an n× n multiplier, in which a specific logic implementation is used for the full-adders, the hardware consists of n(n — 1) full-adders, n22-input and gates, and, in addition, at most 4 extra 2-input and gates and one controllable input. Coincidentally, the multiplier structure of our C-testable DCVS design is the same as the structure of the second gate-level design. However, the DCVS full-adders are implemented differently. Both the hardware and delay overhead for all our C-testable designs are very small and decrease with increasing n. For example, for our three C-testable designs of the 32 by 32 multiplier, the hardware overhead is 2.7% or less and the delay overhead is 2.4% or less.

AB - In this paper some C-testable designs of a carry-save parallel multiplier are presented. Results are given for both the gate-level implementation and the differential cascode voltage switch (DCVS) implementation. DCVS circuits are dynamic CMOS circuits which have the advantage of being protected against test set invalidation due to circuit delays. In the first gate-level design we assume that the full-adders have any arbitrary, irredundant logic implementation. Such a design is C-testable with only 9 test vectors, which detect all single stuck-at faults. For a specific logic implementation of the full-adders, another design is shown to be C-testable with only 6 test vectors. The DCVS design is also C-testable with only 6 test vectors, which detect all detectable stuck-at, stuck-on, and stuck-open faults in the circuit. The hardware for the first gate-level design for an n x n multiplier consists of n(n - 1) full-adders, a summand generator consisting of n22-input and gates, as well as 6 extra 2- or 3-input gates and n extra 2-input ex-or gates to enhance the controllability of the circuit. Two additional controllable inputs are also required for this gate-level design. In the second gate-level design for an n× n multiplier, in which a specific logic implementation is used for the full-adders, the hardware consists of n(n — 1) full-adders, n22-input and gates, and, in addition, at most 4 extra 2-input and gates and one controllable input. Coincidentally, the multiplier structure of our C-testable DCVS design is the same as the structure of the second gate-level design. However, the DCVS full-adders are implemented differently. Both the hardware and delay overhead for all our C-testable designs are very small and decrease with increasing n. For example, for our three C-testable designs of the 32 by 32 multiplier, the hardware overhead is 2.7% or less and the delay overhead is 2.4% or less.

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U2 - 10.1109/43.87603

DO - 10.1109/43.87603

M3 - Article

AN - SCOPUS:0026185635

VL - 10

SP - 932

EP - 942

JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

SN - 0278-0070

IS - 7

ER -