Easily testable DCVS multiplier

Andres R. Takach, Niraj K. Jha

Research output: Contribution to journalConference article

1 Scopus citations

Abstract

Clocked differential cascode voltage switch (DCVS) circuits are dynamic CMOS circuits which have the advantage of being protected against test-set invalidation due to circuit delays. A C-testable DCVS design of a carry-save parallel multiplier is presented. This design is C-testable with only six test vectors which detect all detectable stuck-at, stuck-on, and stuck-open faults in the circuit. The hardware needed for an n × n multiplier consists of n(n-1) full-adders, a summand generator consisting of n2 2-input AND gates, as well as (at most) four extra 2-input AND gates to enhance the controllability of the circuit. An additional controllable input t is required. The design of the multiplier is discussed. The set of vectors to test the individual building blocks of the multiplier is presented. The input assignments to the DCVS multiplier, which result in the application of the appropriate tests to each module, are discussed, and the validity of the test set for detecting the detectable single stuck-at, stuck-open, and stuck-on faults is proved.

Original languageEnglish (US)
Pages (from-to)2732-2735
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume4
StatePublished - Dec 1 1990
Event1990 IEEE International Symposium on Circuits and Systems Part 4 (of 4) - New Orleans, LA, USA
Duration: May 1 1990May 3 1990

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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