Dynamically reconfigurable architecture for fault-tolerant 2D networks-on-chip

Computer Science

• Networks on Chips 100%
• reconfigurable architecture 100%
• Fault Tolerant 100%
• Experimental Result 50%
• fault-tolerance 50%
• Network Performance 50%
• Hardware Overhead 50%
• Longest Path 50%
• Router Architecture 50%
• Communicating Node 50%

Engineering

• Network-on-Chip 100%
• Experimental Result 50%
• Nodes 50%
• Fits and Tolerances 50%
• Hardware Overhead 50%
• Longest Path 50%
• Device Scaling 50%

Keyphrases

• Fault-tolerant Strategy 50%
• Minimal Routing 50%
• Reconfigurable Techniques 50%