Dynamically reconfigurable architecture for fault-tolerant 2D networks-on-chip

With the increasing device scaling in the semiconductor technology, the necessity for designing robust and efficient Networks-on-Chip (NoCs) is more pronounced. The rerouting approach which is employed in most of the fault-tolerant methods causes the network performance to degrade considerably due to taking longer paths and creating hotspots around the faults. In this paper, a dynamically reconfigurable technique is proposed to target fault-tolerance and minimal routing in a unified manner. To accomplish this goal, the router architecture is modified to enable the frequently communicating nodes to bypass the faulty router and communicate through shorter paths. Thus, not only the rerouting is minimized, the connectivity of the network is maintained in the vicinity of faults. The experimental results validate the performance and reliability of the proposed technique with a small hardware overhead.