Dynamic voltage scaling with links for power optimization of interconnection networks

Li Shang, Li Shiuan Peh, Niraj Kumar Jha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

375 Scopus citations

Abstract

Originally developed to connect processors and memories in multicomputers, prior research and design of interconnection networks have focused largely on performance. As these networks get deployed in a wide range of new applications, where power is becoming a key design constraint, we need to seriously consider power efficiency in designing interconnection networks. As the demand for network bandwidth increases, communication links, already a significant consumer of power now, will take up an ever larger portion of total system power budget. In this paper we motivate the use of dynamic voltage scaling (DVS) for links, where the frequency and voltage of links are dynamically adjusted to minimize power consumption. We propose a history-based DVS policy that judiciously adjusts link frequencies and voltages based on past utilization. Our approach realizes up to 6.3× power savings (4.6× on average). This is accompanied by a moderate impact on performance (15.2% increase in average latency before network saturation and 2.5% reduction in throughput.) To the best of our knowledge, this is the first study that targets dynamic power optimization of interconnection networks.

Original languageEnglish (US)
Title of host publicationProceedings - 9th International Symposium on High-Performance Computer Architecture, HPCA 2003
PublisherIEEE Computer Society
Pages91-102
Number of pages12
ISBN (Electronic)0769518710
DOIs
StatePublished - Jan 1 2003
Event9th IEEE International Symposium on High-Performance Computer Architecture, HPCA 2003 - Anaheim, United States
Duration: Feb 8 2003Feb 12 2003

Publication series

NameProceedings - International Symposium on High-Performance Computer Architecture
Volume12
ISSN (Print)1530-0897

Other

Other9th IEEE International Symposium on High-Performance Computer Architecture, HPCA 2003
CountryUnited States
CityAnaheim
Period2/8/032/12/03

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

Keywords

  • Bandwidth
  • Circuits
  • Dynamic voltage scaling
  • Fabrics
  • Frequency
  • IP networks
  • Microprocessors
  • Multiprocessing systems
  • Multiprocessor interconnection networks
  • Voltage control

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