Dynamic programming implementation on array processor architectures

K. I. Diamantaras, W. H. Chou, S. Y. Kung

Research output: Contribution to journalArticlepeer-review


Dynamic Programming (DP) applies to many signal and image processing applications including boundary following, the Viterbi algorithm, dynamic time warping, etc. This paper presents an array processor implementation of generic dynamic programming. Our architecture is a SIMD array attached to a host computer. The processing element of the architecture is based on an ASIC design opting for maximum speed-up. By adopting a torus interconnection network, a dual buffer structure, and a multilevel pipeline, the performance of the DP chip is expected to reach the order of several GOPS. The paper discusses both the dedicated hardware design and the data flow control of the DP chip and the total array.

Original languageEnglish (US)
Pages (from-to)27-35
Number of pages9
JournalJournal of VLSI Signal Processing Systems for Signal, Image, and Video Technology
Issue number1
StatePublished - 1996

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Information Systems
  • Electrical and Electronic Engineering


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