Duet: Creating Harmony between Processors and Embedded FPGAs

Ang Li, August Ning, David Wentzlaff

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

The demise of Moore's Law has led to the rise of hardware acceleration. However, the focus on accelerating stable algorithms in their entirety neglects the abundant fine-grained acceleration opportunities available in broader domains and squanders host processors' compute power.This paper presents Duet, a scalable, manycore-FPGA architecture that promotes embedded FPGAs (eFPGA) to be equal peers with processors through non-intrusive, bi-directionally cache-coherent integration. In contrast to existing CPU-FPGA hybrid systems in which the processors play a supportive role, Duet unleashes the full potential of both the processors and the eFPGAs with two classes of post-fabrication enhancements: fine-grained acceleration, which partitions an application into small tasks and offloads the frequently-invoked, compute-intensive ones onto various small accelerators, leveraging the processors to handle dynamic control flow and less accelerable tasks; hardware augmentation, which employs eFPGA-emulated hardware widgets to improve processor efficiency or mitigate software overheads in certain execution models.An RTL-level implementation of Duet is developed to evaluate the architecture with high fidelity. Experiments using synthetic benchmarks show that Duet can reduce the processor-accelerator communication latency by up to 82% and increase the bandwidth by up to 9.5x. The RTL implementation is further evaluated with seven application benchmarks, achieving 1.5-24.9x speedup.

Original languageEnglish (US)
Title of host publication2023 IEEE International Symposium on High-Performance Computer Architecture, HPCA 2023 - Proceedings
PublisherIEEE Computer Society
Pages745-758
Number of pages14
ISBN (Electronic)9781665476522
DOIs
StatePublished - 2023
Event29th IEEE International Symposium on High-Performance Computer Architecture, HPCA 2023 - Montreal, Canada
Duration: Feb 25 2023Mar 1 2023

Publication series

NameProceedings - International Symposium on High-Performance Computer Architecture
Volume2023-February
ISSN (Print)1530-0897

Conference

Conference29th IEEE International Symposium on High-Performance Computer Architecture, HPCA 2023
Country/TerritoryCanada
CityMontreal
Period2/25/233/1/23

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

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