Die-level leakage power analysis of FinFET circuits considering process variations

Keyphrases

• Die-level 100%
• Leakage Power Analysis 100%
• FinFET Circuits 100%
• Independent Gate 66%
• Logic Cell 66%
• Yield Point 33%
• Current Distribution 33%
• Diminishing Returns 33%
• Low Power Mode 33%
• Latin Hypercube Sampling 33%
• Benchmark Circuits 33%
• Quadtree 33%
• FinFET Devices 33%
• Planar CMOS 33%
• Tree Grid 33%
• Short Channel 33%
• Leakage Probability 33%
• Channel Characteristics 33%
• Sentaurus TCAD 33%
• NOR Gate 33%
• Standard Logic Cells 33%
• Combinational Logic Circuits 33%
• Synthetic Strategies 33%
• Stacked Devices 33%
• Quasi-Monte Carlo 33%

Engineering

• Yield Point 33%
• Latin-Hypercube Sampling 33%
• Power Mode 33%
• Current Distribution 33%