Development of an optimizing compiler for a Fujitsu fixed-point digital signal processor

Sreeranga P. Rajan; Masahiro Fujita; Ashok Sudarsanam; Sharad Malik

doi:10.1145/301177.301184

Development of an optimizing compiler for a Fujitsu fixed-point digital signal processor

Sreeranga P. Rajan, Masahiro Fujita, Ashok Sudarsanam, Sharad Malik

Research output: Contribution to conference › Paper › peer-review

3 Scopus citations

Abstract

A common design methodology for embedded DSP systems is the integration of one or more digital signal processors (DSPs), program memory, and ASIC circuitry onto a single IC. Consequently, program memory size being limited, the criterion for optimality is that the embedded software must be very dense. We describe the development of an optimizing compiler, based on a retargetable compiler infrastructure, for the Fujitsu Elixir, a fixed-point DSP that is primarily used in cellular telephones. For small DSP benchmark programs (25-90 lines of C code), the average ratio of the size of compiler-generated code to the size of hand-written assembly code is 1.18. For a much larger program (more than 800 lines of C code), the ratio of the size of compiled code to the size of hand-written code is similar (1.14).

Original language	English (US)
Pages	2-6
Number of pages	5
DOIs	https://doi.org/10.1145/301177.301184
State	Published - 1999
Externally published	Yes
Event	Proceedings of the 1999 7th International Conference on Hardware/Software Codesign (CODES'99) - Rome, Italy Duration: May 3 1999 → May 5 1999

Conference

Conference	Proceedings of the 1999 7th International Conference on Hardware/Software Codesign (CODES'99)
City	Rome, Italy
Period	5/3/99 → 5/5/99

All Science Journal Classification (ASJC) codes

Hardware and Architecture

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10.1145/301177.301184

Cite this

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abstract = "A common design methodology for embedded DSP systems is the integration of one or more digital signal processors (DSPs), program memory, and ASIC circuitry onto a single IC. Consequently, program memory size being limited, the criterion for optimality is that the embedded software must be very dense. We describe the development of an optimizing compiler, based on a retargetable compiler infrastructure, for the Fujitsu Elixir, a fixed-point DSP that is primarily used in cellular telephones. For small DSP benchmark programs (25-90 lines of C code), the average ratio of the size of compiler-generated code to the size of hand-written assembly code is 1.18. For a much larger program (more than 800 lines of C code), the ratio of the size of compiled code to the size of hand-written code is similar (1.14).",

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doi = "10.1145/301177.301184",

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AU - Rajan, Sreeranga P.

AU - Fujita, Masahiro

AU - Sudarsanam, Ashok

AU - Malik, Sharad

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Y1 - 1999

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AB - A common design methodology for embedded DSP systems is the integration of one or more digital signal processors (DSPs), program memory, and ASIC circuitry onto a single IC. Consequently, program memory size being limited, the criterion for optimality is that the embedded software must be very dense. We describe the development of an optimizing compiler, based on a retargetable compiler infrastructure, for the Fujitsu Elixir, a fixed-point DSP that is primarily used in cellular telephones. For small DSP benchmark programs (25-90 lines of C code), the average ratio of the size of compiler-generated code to the size of hand-written assembly code is 1.18. For a much larger program (more than 800 lines of C code), the ratio of the size of compiled code to the size of hand-written code is similar (1.14).

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Development of an optimizing compiler for a Fujitsu fixed-point digital signal processor

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