Development of an optimizing compiler for a Fujitsu fixed-point digital signal processor

Sreeranga P. Rajan, Masahiro Fujita, Ashok Sudarsanam, Sharad Malik

Research output: Contribution to journalArticle

3 Scopus citations

Abstract

A common design methodology for embedded DSP systems is the integration of one or more digital signal processors (DSPs), program memory, and ASIC circuitry onto a single IC. Consequently, program memory size being limited, the criterion for optimality is that the embedded software must be very dense. We describe the development of an optimizing compiler, based on a retargetable compiler infrastructure, for the Fujitsu Elixir, a fixed-point DSP that is primarily used in cellular telephones. For small DSP benchmark programs (25-90 lines of C code), the average ratio of the size of compiler-generated code to the size of hand-written assembly code is 1.18. For a much larger program (more than 800 lines of C code), the ratio of the size of compiled code to the size of hand-written code is similar (1.14).

Original languageEnglish (US)
Pages (from-to)2-6
Number of pages5
JournalHardware/Software Codesign - Proceedings of the International Workshop
StatePublished - Jan 1 1999
Externally publishedYes

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

Fingerprint Dive into the research topics of 'Development of an optimizing compiler for a Fujitsu fixed-point digital signal processor'. Together they form a unique fingerprint.

  • Cite this