Design of ultra-low-leakage logic gates and flip-flops in high-performance FinFET technology

Ajay N. Bhoj, Niraj Kumar Jha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

26 Scopus citations

Abstract

Multi-gate CMOS devices promise to usher an era of transistors with good electrostatic integrity at the sub-22nm nodes, which makes it essential to rethink traditional approaches to designing low-leakage digital logic and sequential elements formerly used in high-performance planar single-gate technologies. In the current work, we explore the design space of symmetric (Symm-ΦG) and asymmetric gate workfunction (Asymm- ΦG) FinFET logic gates, latches, and flip-flops for optimal trade-offs in leakage vs. delay and temperature in a high-performance FinFET technology. We demonstrate, using mixed-mode Sentaurus technology computer-aided design (TCAD) device simulations, that Asymm-ΦG shorted-gate n/p-FinFETs, which use both workfunctions corresponding to typical high-performance n/p-FinFETs, yield over two orders of magnitude lower leakage without excessive degradation in on-state current, in comparison to Symm-ΦG shorted-gate (SG) FinFETs, placing them in a better position than back-gate biased independent-gate (IG) FinFETs for leakage reduction. Results for elementary logic gates like INV, NAND2, NOR2, XOR2, and XNOR2 using Asymm-ΦG SG-mode FinFETs indicate that they are more optimally located in the leakage-delay spectrum in comparison to the most versatile configurations possible by mixing corresponding Symm-G SG- and IG-mode FinFETs. Latches and flip-flops, however, require an astute combination of Symm-ΦG and Asymm-ΦG FinFETs to optimize leakage, delay, and setup time simultaneously.

Original languageEnglish (US)
Title of host publicationProceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011
Pages695-702
Number of pages8
DOIs
StatePublished - Jun 22 2011
Event12th International Symposium on Quality Electronic Design, ISQED 2011 - Santa Clara, CA, United States
Duration: Mar 14 2011Mar 16 2011

Publication series

NameProceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011

Other

Other12th International Symposium on Quality Electronic Design, ISQED 2011
CountryUnited States
CitySanta Clara, CA
Period3/14/113/16/11

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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