Abstract
The sequential behavior of CMOS logic circuits in the presence of stuck-open faults requires that an initialization input followed by a test input be applied to detect such a fault. However, a test set based on the assumption that delays through all gates and interconnections are zero can be invalidated in the presence of arbitrary delays in the circuit. The authors present a necessary and sufficient condition for the existence of a test set, which cannot be invalidated under arbitrary delays, for an AND-OR or OR-AND CMOS realization for any given function. They also introduce a hybrid CMOS realization which, for any given function, is guaranteed to have a valid test set under arbitrary delays.
Original language | English (US) |
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Journal | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Volume | CAD-4 |
Issue number | 3 |
State | Published - 1985 |
Externally published | Yes |
All Science Journal Classification (ASJC) codes
- Software
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering