DESIGN OF TESTABLE CMOS LOGIC CIRCUITS UNDER ARBITRARY DELAYS.

Niraj Kumar Jha, Jacob A. Abraham

Research output: Contribution to journalArticle

Abstract

The sequential behavior of CMOS logic circuits in the presence of stuck-open faults requires that an initialization input followed by a test input be applied to detect such a fault. However, a test set based on the assumption that delays through all gates and interconnections are zero can be invalidated in the presence of arbitrary delays in the circuit. The authors present a necessary and sufficient condition for the existence of a test set, which cannot be invalidated under arbitrary delays, for an AND-OR or OR-AND CMOS realization for any given function. They also introduce a hybrid CMOS realization which, for any given function, is guaranteed to have a valid test set under arbitrary delays.

Original languageEnglish (US)
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
VolumeCAD-4
Issue number3
StatePublished - Jan 1 1985
Externally publishedYes

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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