Design of robustly testable static CMOS parity trees derived from binary decision diagrams

Niraj Kumar Jha; Qiao Tong

Design of robustly testable static CMOS parity trees derived from binary decision diagrams

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A robustly testable design of static CMOS parity trees is presented. A test set for such a tree which cannot be invalidated in the presence of arbitrary timing skews and/or circuit delays can be derived. The constituents of the parity tree are static CMOS EXCLUSIVE-OR (EX-OR) gates, which are constructed from their corresponding binary decision diagrams (BDDs). The EX-OR gates in the tree can have any number of inputs. The robust test set detects all the single stuck-open, stuck-on, and stuck-at faults when both logic and current monitoring are done. It is shown that such implementations of parity trees are testable with a test set of size O(log_kn), where n is the number of primary inputs and k is a circuit parameter.

Original language	English (US)
Title of host publication	Proceedings - IEEE International Conference on Computer Design
Subtitle of host publication	VLSI in Computers and Processors
Publisher	Publ by IEEE
Pages	103-106
Number of pages	4
ISBN (Print)	O81862079X
State	Published - Sep 1 1990
Event	Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '90 - Cambridge, MA, USA Duration: Sep 17 1990 → Sep 19 1990

Other

Other	Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '90
City	Cambridge, MA, USA
Period	9/17/90 → 9/19/90

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

Cite this

@inproceedings{d2080a11fa2d49d383d84813a7f4d7d9,

title = "Design of robustly testable static CMOS parity trees derived from binary decision diagrams",

abstract = "A robustly testable design of static CMOS parity trees is presented. A test set for such a tree which cannot be invalidated in the presence of arbitrary timing skews and/or circuit delays can be derived. The constituents of the parity tree are static CMOS EXCLUSIVE-OR (EX-OR) gates, which are constructed from their corresponding binary decision diagrams (BDDs). The EX-OR gates in the tree can have any number of inputs. The robust test set detects all the single stuck-open, stuck-on, and stuck-at faults when both logic and current monitoring are done. It is shown that such implementations of parity trees are testable with a test set of size O(logkn), where n is the number of primary inputs and k is a circuit parameter.",

author = "Jha, {Niraj Kumar} and Qiao Tong",

year = "1990",

month = sep,

day = "1",

language = "English (US)",

isbn = "O81862079X",

pages = "103--106",

booktitle = "Proceedings - IEEE International Conference on Computer Design",

publisher = "Publ by IEEE",

note = "Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '90 ; Conference date: 17-09-1990 Through 19-09-1990",

}

Jha, NK & Tong, Q 1990, Design of robustly testable static CMOS parity trees derived from binary decision diagrams. in Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. Publ by IEEE, pp. 103-106, Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '90, Cambridge, MA, USA, 9/17/90.

TY - GEN

T1 - Design of robustly testable static CMOS parity trees derived from binary decision diagrams

AU - Jha, Niraj Kumar

AU - Tong, Qiao

PY - 1990/9/1

Y1 - 1990/9/1

N2 - A robustly testable design of static CMOS parity trees is presented. A test set for such a tree which cannot be invalidated in the presence of arbitrary timing skews and/or circuit delays can be derived. The constituents of the parity tree are static CMOS EXCLUSIVE-OR (EX-OR) gates, which are constructed from their corresponding binary decision diagrams (BDDs). The EX-OR gates in the tree can have any number of inputs. The robust test set detects all the single stuck-open, stuck-on, and stuck-at faults when both logic and current monitoring are done. It is shown that such implementations of parity trees are testable with a test set of size O(logkn), where n is the number of primary inputs and k is a circuit parameter.

AB - A robustly testable design of static CMOS parity trees is presented. A test set for such a tree which cannot be invalidated in the presence of arbitrary timing skews and/or circuit delays can be derived. The constituents of the parity tree are static CMOS EXCLUSIVE-OR (EX-OR) gates, which are constructed from their corresponding binary decision diagrams (BDDs). The EX-OR gates in the tree can have any number of inputs. The robust test set detects all the single stuck-open, stuck-on, and stuck-at faults when both logic and current monitoring are done. It is shown that such implementations of parity trees are testable with a test set of size O(logkn), where n is the number of primary inputs and k is a circuit parameter.

UR - http://www.scopus.com/inward/record.url?scp=0025487080&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0025487080&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0025487080

SN - O81862079X

SP - 103

EP - 106

BT - Proceedings - IEEE International Conference on Computer Design

PB - Publ by IEEE

T2 - Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '90

Y2 - 17 September 1990 through 19 September 1990

ER -

Design of robustly testable static CMOS parity trees derived from binary decision diagrams

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