Design of robustly testable static CMOS parity trees derived from binary decision diagrams

Niraj Kumar Jha, Qiao Tong

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A robustly testable design of static CMOS parity trees is presented. A test set for such a tree which cannot be invalidated in the presence of arbitrary timing skews and/or circuit delays can be derived. The constituents of the parity tree are static CMOS EXCLUSIVE-OR (EX-OR) gates, which are constructed from their corresponding binary decision diagrams (BDDs). The EX-OR gates in the tree can have any number of inputs. The robust test set detects all the single stuck-open, stuck-on, and stuck-at faults when both logic and current monitoring are done. It is shown that such implementations of parity trees are testable with a test set of size O(logkn), where n is the number of primary inputs and k is a circuit parameter.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Conference on Computer Design
Subtitle of host publicationVLSI in Computers and Processors
PublisherPubl by IEEE
Pages103-106
Number of pages4
ISBN (Print)O81862079X
StatePublished - Sep 1 1990
EventProceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '90 - Cambridge, MA, USA
Duration: Sep 17 1990Sep 19 1990

Other

OtherProceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '90
CityCambridge, MA, USA
Period9/17/909/19/90

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • Cite this

    Jha, N. K., & Tong, Q. (1990). Design of robustly testable static CMOS parity trees derived from binary decision diagrams. In Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors (pp. 103-106). Publ by IEEE.