@inproceedings{d2080a11fa2d49d383d84813a7f4d7d9,
title = "Design of robustly testable static CMOS parity trees derived from binary decision diagrams",
abstract = "A robustly testable design of static CMOS parity trees is presented. A test set for such a tree which cannot be invalidated in the presence of arbitrary timing skews and/or circuit delays can be derived. The constituents of the parity tree are static CMOS EXCLUSIVE-OR (EX-OR) gates, which are constructed from their corresponding binary decision diagrams (BDDs). The EX-OR gates in the tree can have any number of inputs. The robust test set detects all the single stuck-open, stuck-on, and stuck-at faults when both logic and current monitoring are done. It is shown that such implementations of parity trees are testable with a test set of size O(logkn), where n is the number of primary inputs and k is a circuit parameter.",
author = "Jha, {Niraj K.} and Qiao Tong",
year = "1990",
month = sep,
language = "English (US)",
isbn = "O81862079X",
series = "Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors",
publisher = "Publ by IEEE",
pages = "103--106",
booktitle = "Proceedings - IEEE International Conference on Computer Design",
note = "Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '90 ; Conference date: 17-09-1990 Through 19-09-1990",
}