Design of Robustly Testable Combinational Logic Circuits

It is known that circuit delays and timing skews in input vector changes influence choice of tests to detect delay faults. Tests for stuck-open faults in CMOS logic circuits can also be invalidated by circuit delays and timing skews in input vector changes. Tests that detect modeled faults independent of the delays in the circuit under test are called robust tests. In this paper we propose an integrated approach to the design of combinational logic circuits in which all path delay faults and multiple line stuck-at, transistor stuck-open faults are detectable by robust tests. We also demonstrate that the proposed method guarantees the design of CMOS logic circuits in which all path delay faults are locatable.