Design of logic gates and flip-flops in high-performance finFET technology

Ajay N. Bhoj, Niraj K. Jha

Research output: Contribution to journalArticlepeer-review

60 Scopus citations


With the emergence of nonplanar CMOS devices at the 22-nm node and beyond, it is highly likely that multigate device adoption will occur in a high-performance process technology, owing to the increased performance and area benefits. In this paper, for the first time, we evaluate symmetric (Symm-ΦG) and asymmetric (Asymm-ΦG) gate-workfunction FinFETs head to head in a high-performance process, using technology computer-aided design 3-D device simulations. We demonstrate that Asymm-ΦG shorted-gate (a-SG) n/p-FinFETs, which use both workfunctions corresponding to typical high-performance metal-gate n/p-FinFETs, are promising, as they can yield over two orders of magnitude lower leakage without excessive degradation in ON-state current, in comparison to Symm-ΦG shorted-gate (SG) FinFETs, placing them in a better position than back-gate biased independent-gate (IG) FinFETs for leakage reduction. Thereafter, we explore the design space of FinFET logic gates, latches, and flip-flops, for optimal tradeoffs in leakage versus delay and temperature, using mixed-mode 2-D device simulations. Elementary logic gates (such as INV, NAND2, NOR2, XOR2, and XNOR2) using Asymm-ΦG SG-mode FinFETs appear to be located optimally in the leakage-delay spectrum, in comparison to the most versatile configurations possible by mixing corresponding Symm-ΦG SG-and IG-mode FinFETs. Latches and flip-flops, however, require an astute combination of Symm-ΦG and Asymm-ΦG FinFETs to optimize leakage, delay, and setup time simultaneously.

Original languageEnglish (US)
Article number6414664
Pages (from-to)1975-1988
Number of pages14
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number11
StatePublished - 2013

All Science Journal Classification (ASJC) codes

  • Software
  • Electrical and Electronic Engineering
  • Hardware and Architecture


  • Device simulation
  • FinFETs
  • flip-flops
  • leakage power
  • logic gate
  • multigate device


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