Design of efficient content addressable memories in high-performance FinFET technology

Debajit Bhattacharya, Ajay N. Bhoj, Niraj K. Jha

Research output: Contribution to journalArticle

7 Scopus citations

Abstract

Content addressable memories (CAMs) enable high-speed parallel search operations in table lookup-based applications, such as Internet routers and processor caches. Traditional CAM design has always suffered from the high dynamic power consumption associated with its large and active parallel hardware. However, deeply scaled technology nodes, with multigate devices replacing planar MOSFETs, are expected to bring new tradeoffs to CAM design. FinFET, a vertical-channel gate-wrap-around double-gate device, has emerged as the best alternative to planar MOSFET. In this brief, for the first time, we explore the design space of symmetric and asymmetric gate-workfunction FinFET CAMs. We propose several design alternatives and evaluate them in terms of their dc and transient metrics for different mismatch probabilities using technology computer-aided design simulations with 22-nm FinFET devices. We also propose two orthogonal layout styles for CAM design and show that one of them (vertical-search line) outperforms the other (vertical-match line) in terms of total power (22.3%) and search delay (5.8%).

Original languageEnglish (US)
Article number6857432
Pages (from-to)963-967
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume23
Issue number5
DOIs
StatePublished - May 1 2015

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Keywords

  • Content addressable memories (CAMs)
  • FinFET
  • parasitic extraction
  • technology computer-aided design (TCAD).

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